Webcast: 3-D Integration: What Direction Will It Take?
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Originally broadcast September 5, 2007
Imagine a 1000x improvement in speed and 100x improvement in power. That’s the incredible promise of 3-D integration, which involves thinning the wafer or die and then stacking and electrically connecting them. One challenge is that there are many different ways to accomplish 3-D integration, each with different cost implications. This webcast examines the processes used to create 3-D structures, including wafer thinning, alignment and bonding, and the processes for creating through-silicon vias (TSVs), including deep silicon etching, depositing dielectric diffusion barriers and metal electroplating. Panelists will also look at the devices driving 3-D integration approaches.
Moderator:
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Laura Peters Lead Technical Editor Semiconductor International |
Panelists:
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Bart Swinnen Program Manager IMEC |
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Sitaram Arkalgud Interconnect Division Director Sematech |
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Mahadevan Iyer Microsystems Packaging Research Center, Georgia Institute of Technology |
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Posted: Aug 10, 2007