During this Webcast, Gennum Corporation, an emerging fabless semiconductor organization, will discuss how they are planning to leverage IT through best practices to prepare for and drive future growth. You will also hear from SAP as they discuss their industry solution for the semiconductor industry. In addition, Bristlecone will share their perspectives on modeling the SAP solution to address the unique requirements of the fabless semiconductor companies.  more >>

Today leading semiconductor companies employ focused ion beam (FIB) circuit editing to speed up design validation and performance optimization. FIBs can remove and deposit insulator and conductor materials to "re-wire" around flaws or to make circuit performance improvements. The material removal and deposition is done with high precision using an ion beam together with a variety of chemical gases. FIB circuit editing eliminates iterative cycles of prototype testing and mask modification.  more >>

Experts from FEI Company and the National Renewable Energy Laboratory (NREL) will discuss new analysis and characterization capabilities for novel materials and devices. Dr. Manuel Romero of NREL will present recent advances in scanning electron microscopy (SEM) that can be applied to state-of-the-art materials in the solar field, and Dr. Richard Young of FEI will discuss how you can maximize the analytical performance and flexibility of your SEM.  more >>

When you're working at advanced geometries, you'll need tools and techniques that give you better resolution to find and analyze previously hidden failures. This seminar will show you how to combine in-situ probing techniques with scanning electron microscopy (SEM) or DualBeam tools to gain superior results at 90nm and below.  more >>

Join SAP and NVIDIA for a Webcast that explores the challenges fabless semiconductors face in an outsourced manufacturing environment. Learn how NVIDIA leveraged “Fabless” Outsourced Manufacturing best practices for visibility and control of their globally outsourced supply chain, and the benefits they have achieved by managing the process by exception. Attend this important online event and see why more than 3,500 high-tech companies run their businesses with SAP software.  more >>

In semiconductor device and process characterization and model verification, wafer-level impedance measurements, particularly C-V measurements, are a necessity, especially in a world of high-k, ultra-thin and low-k dielectrics. Such measurements allow the test engineer to get critical information about the device under test (DUT) such as gate oxide thickness (tOX) and threshold voltage (VT).  more >>

In the past, making wafer-level measurements on power devices meant extra costs and delays in development schedules, unreliable or inaccurate data, and considerable safety risks. Not any longer. Now you can perform on-wafer measurements up to 60A or 3,000V and eliminate the need for packaging prior to characterization.  more >>

Semiconductor manufacturers continue to push the thickness of wafers and devices down. This is driven by a need for innovative packaging options such as 3-D packaging as well as by enabling even higher device performance or lower power consumption. However, there has yet to emerge a clear manufacturing process for handling ultra thin wafers.  more >>