Although advanced copper interconnects have been enabled by the damascene approach, the increasingly dense integration requirements, together with feature shrinks are driving deposition processes to evolve. It is uncertain how extendible copper deposition processes will be at the 32 nm node and beyond. A panel of industry experts will discuss possible options and solutions for metallization schemes.  more >>

Recorded as a live panel at Sematech's 2008 Surface Preparation and Cleaning Conference (SPCC) in Austin, Texas, the discussion will focus on front-end-of-line (FEOL) wafer cleaning and photoresist strip challenges and solutions for the 45 and 32 nm device generations. Industry experts present the real-world problems and solutions surrounding a plethora of new materials being used and considered, including related environmental issues.  more >>

Through-silicon via (TSV) processes are already in volume manufacturing for CMOS image sensors, but it's not yet clear if the costs will be manageable for high-volume memory and logic 3-D chip stacking. A panel of experts will discuss the various etch, deposition and plating processes required for fabricating TSVs, focusing on unsolved manufacturability challenges. The role of wafer thinning and carriers, as well as reliability, design and test issues, will also be covered.  more >>

Immersion is way past the gee-whiz phase, and chipmakers are working to have it implemented beginning with the 45 nm technology node. What hurdles still need to be overcome to make the technology truly suitable for 45 nm production? What types of devices are most likely to make use of immersion first?  more >>

The International Technology Roadmap for Semiconductors (ITRS) was up for a major revision in 2007, and was released to the public in December. In this webcast, a key organizer of the roadmap will explain the important changes relative to past years and significant additions to the roadmap, including the discussion of More than Moore, reasons for the changes, and ways that the roadmap should be interpreted.  more >>

A variety of new substrates are finding applications in semiconductors, solar cells, optoelectronics and displays. This webcast will have a special emphasis on silicon-on-insulator (SOI) substrates and the devices that use them, while also exploring the myriad of other templated and epitaxial materials being investigated and optimized for their distinct properties.  more >>

The introduction of new materials such as ultralow-k films, less forgiving processes, and new structures demand new metrology techniques for interconnect and gate etch. Although mature techniques like OCD and scatterometry, as well as CD-SEM, continue successfully to provide the necessary metrology, some applications will require specific types of metrology, which is expected to lead to an overall requirement for additional, possibly revolutionary, metrology capabilities.  more >>

While continued scaling through lithography has traditionally been the domain of shorter-wavelength lightsources, it is now dominated by increasingly complex photomasks, and the software required to handle that complexity. Hear experts detail the challenges and solutions associated with this change.  more >>

Imagine a 1000x improvement in speed and 100x improvement in power. That’s the incredible promise of 3-D integration, which involves thinning the wafer or die and then stacking and electrically connecting them. This webcast examines the processes used to create 3-D structures and through-silicon vias (TSVs). Panelists will also look at the devices driving 3-D integration approaches.  more >>

As chip speed and functionality increase, so too does the need for reliable methods to connect higher and higher levels of input/outputs from the chip to the outside world. Compounded by the demand for lead-free processing, the industry is developing new approaches to packaging, including wafer bumping (and underbump metallization), gold stud bumping, eletroplated studs and the IBM/SUSS C4NP process. Experts will discuss these and other approaches, with a panel moderated by Editor-in-Chief Pete Singer.  more >>