All Webcasts
Intel's Journey With SAP Customer Relationship Management (SAP CRM)
October 1, 2008 7:20pm CDT
Learn first-hand how Intel leveraged SAP CRM for greater agility to support business growth, while achieving 15%+ year-over-year cost savings. more >>
Posted: Aug 27, 2008 | Permalink
Evolving CMP for Scaling
September 16, 2008 10:44pm CDT
Shrinking critical dimensions with correspondingly thinner metal layers and shorter stack heights have been alerting all sectors to rethink traditional chemical mechanical planarization (CMP) chemistries and processes. Panelists will discuss the demands for low-damage processes and excellent uniformity as well as new ways to address those challenges, particularly in copper metallization and barrier steps for interconnects. more >>
Posted: Aug 19, 2008 | Permalink
XHR: SEM Like You've Never Seen Before
July 10, 2008 7:29pm CDT
Sign up now for this webcast and find out what it means to see SEM like you've never seen before. Advanced process development and process engineering groups have recently struggled to get the images and data they need from SEM platforms. But recent advancements in SEM technology have brought new levels of performance and flexibility not previously available to the lab. more >>
Posted: May 21, 2008 | Permalink
Innovation at Risk — Intellectual Property Challenges and Opportunities
June 17, 2008 9:13pm CDT
Semiconductor equipment and materials suppliers face serious and mounting challenges in intellectual property (IP) protection, with adverse economic consequences for the entire microelectronics industry, according to a new white paper published by SEMI. The report provides a detailed study of various IP challenges facing the equipment and materials industry and offers recommendations for improving the situation. more >>
Posted: May 27, 2008 | Permalink
SIA Semiconductor Industry Forecast Mid-Year Update 2008-2011
June 11, 2008 9:17pm CDT
Tune in to this mid-year webcast for the latest SIA forecast of global semiconductor sales through 2011. SIA President George Scalise will offer comments and analysis of what may lie ahead for the global chip industry. more >>
Posted: May 21, 2008 | Permalink
Litho Forum Survey: EUV by 2016?
June 3, 2008 10:47pm CDT
The lithography industry is under pressure to develop the technologies needed to continue with transistor scaling - whether that's EUV, double patterning, nanoimprint, high-index immersion, maskless, or all of the above. Find out what industry experts have to say about the readiness of future lithography techniques in this presentation of the full results of Sematech's Litho Forum survey. more >>
Posted: May 7, 2008 | Permalink
Can Copper Deposition Break the 32 nm Barrier?
May 21, 2008 12:24am CDT
Although advanced copper interconnects have been enabled by the damascene approach, the increasingly dense integration requirements, together with feature shrinks are driving deposition processes to evolve. It is uncertain how extendible copper deposition processes will be at the 32 nm node and beyond. A panel of industry experts will discuss possible options and solutions for metallization schemes. more >>
Posted: Apr 15, 2008 | Permalink
Wafer Cleaning Solutions for 45 and 32 nm
April 15, 2008 7:04am CDT
Recorded as a live panel at Sematech's 2008 Surface Preparation and Cleaning Conference (SPCC) in Austin, Texas, the discussion will focus on front-end-of-line (FEOL) wafer cleaning and photoresist strip challenges and solutions for the 45 and 32 nm device generations. Industry experts present the real-world problems and solutions surrounding a plethora of new materials being used and considered, including related environmental issues. more >>
Posted: Apr 2, 2008 | Permalink
Rewiring Chips with FIB Circuit Edit: Speed-Up Design Validation & Performance Optimization
April 9, 2008 7:31pm CDT
Today leading semiconductor companies employ focused ion beam (FIB) circuit editing to speed up design validation and performance optimization. FIBs can remove and deposit insulator and conductor materials to "re-wire" around flaws or to make circuit performance improvements. The material removal and deposition is done with high precision using an ion beam together with a variety of chemical gases. FIB circuit editing eliminates iterative cycles of prototype testing and mask modification. more >>
Posted: Mar 4, 2008 | Permalink
Through-Silicon Vias: Ready for Prime Time?
March 25, 2008 7:06am CDT
Through-silicon via (TSV) processes are already in volume manufacturing for CMOS image sensors, but it's not yet clear if the costs will be manageable for high-volume memory and logic 3-D chip stacking. A panel of experts will discuss the various etch, deposition and plating processes required for fabricating TSVs, focusing on unsolved manufacturability challenges. The role of wafer thinning and carriers, as well as reliability, design and test issues, will also be covered. more >>
Posted: Feb 20, 2008 | Permalink
