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RSS   Wafer Processing

The latest news and information on major semiconductor manufacturing process steps, including etch, deposition, epitaxy, chemical mechanical planarization (CMP) and thermal processing.

  • TSMC Begins Production of 40 nm Designs
    David Lammers, News Editor - 11/17/2008
     TSMC said it is now in production of 40 nm designs for a wide variety of customers, ranging from Altera to Sun Microsystems. Although Qualcomm and others have used a TSMC 45 nm process, TSMC Vice President Di Ma said the company developed an IP platform and design support ecosystem for the 40 nm design rules. More

  • Applied Announces TSV Etcher, In-Fab Mask Inspection Capability
    David Lammers, News Editor - 12/01/2008
     Applied Materials Inc. announced its Silvia deep silicon etcher for creation of the smooth sidewalls required for 3-D interconnects. Also, the company said it is offering a new version of its Aera2 mask inspection tool for use within a fab’s lithography cell, rather than at an external mask shop. The Aera2 for Lithography system is needed for double patterning, where mask critical dimensions must be closely watched, the compay said. More
  • SUSS MicroTec Names New CEO
    Staff - 11/25/2008
     Frank Averdung, currently managing director at Carl Zeiss SMS, will move into the CEO position June 1. SUSS MicroTec let its previous CEO go in early October. More
  • IBM Offers 45 nm SOI Foundry Solution
    David Lammers, News Editor - 11/10/2008
     IBM is offering a 45 nm SOI foundry solution to customers seeking to reduce active power consumption. ARM developed an SOI standard cell library, in conjunction with SOI wafer vendor Soitec, that eases SOI designs. Chartered will provide a second-source foundry capability for high-volume SOI customers. More
  • Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
    Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif. - 11/01/2008
     Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes. More
  • Resistivity Reduction Enables Tungsten Scaling
    Frank Huang, Anand Chandrashekar and Michal Danek, Novellus Systems Inc., San Jose - 11/01/2008
     As features shrink beyond 32 nm, conventional pulsed nucleation layer (PNL) will not provide the necessary resistivity performance. Tungsten nucleation and CVD fill developments can extend ALD tungsten to 2X nm features and provide needed resistivity. More
  • SMIC, UMC cut capexs
    By Suzanne Deffree, Managing Editor, News - 10/29/2008
     Amid losses and poor visibility, the two foundries separately announce capex reductions while reporting on Q3 numbers. More
  • Logic Technologies Face Off at IEDM
    David Lammers, News Editor - 10/28/2008
     At the International Electron Devices Meeting (IEDM) planned for Dec. 15-17 in San Francisco, IBM and its partners AMD and Freescale will present a thin SOI technology used to create a 22 nm functional SRAM with a cell size of 0.1 µm2. Intel researchers will detail their 32 nm logic platform, which delivers drive currents of 1.55 mA/µm for the NMOS and 1.21 mA/µm for the PMOS transistors. More
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David Lammers
Views on News
David Lammers, News Editor, Semiconductor International
October 6, 2008
IBM And The All-In Bet on High-K
The debate about the worthiness of high-k/metal gate technology brought to mind what ...
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Alexander E. Braun
The Measure of All Things
Alexander E. Braun, Senior Editor, Semiconductor International
July 14, 2008
Standalone Pushes Optical CD Boundaries
Semiconductor manufacturers face tough process and business challenges. On one hand t...
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David Lammers
Views on News
David Lammers, News Editor, Semiconductor International
June 27, 2008
IBM@45: eDRAM, Si! High-k, No
It now appears that IBM Corp. plans to implement a high-bandwidth silicon-on-insulato...
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Laura Peters
Float Zone
Laura Peters, Editor-in-Chief, Semiconductor International
June 16, 2008
What's With the Name?
Welcome to the debut of my very own blog, the Float Zone. Float zone wafers first cam...
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Technical Articles

    Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif., 11/01/2008
 Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes....

    Resistivity Reduction Enables Tungsten Scaling
Frank Huang, Anand Chandrashekar and Michal Danek, Novellus Systems Inc., San Jose, 11/01/2008
 As features shrink beyond 32 nm, conventional pulsed nucleation layer (PNL) will not provide the necessary resistivity performance. Tungsten nucleation and CVD fill developments can extend ALD tungsten to 2X nm features and provide needed resistivity....

    Yale’s T.P. Ma Proposes Unipolar CMOS
David Lammers, News Editor, 10/08/2008
 Professor T.P Ma of Yale University has proposed a new type of CMOS, named Unipolar CMOS, that would use electrons in both channels. “All I am doing,” Ma said, “is replacing the conventional p-channel by an n-channel transistor that has a negative threshold voltage.” Ma, who won the IEEE Andrew Grove award in 2005, said Unipolar CMOS would gain a speed advantage by not using the slower holes as carriers. Density would improve by using a shared contact....

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