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2009 PC outlook slashed on credit crunch
Single-digit PC unit shipment growth of only 4.3% is expected next year as IT equipment purchases take a back seat to "real issues," like paying staff or making rising mortgage payments, according to iSuppli.

NXP targets medical market with wireless communication partnership
Medical electronics is one of the fastest growing areas of semiconductor development and is becoming increasingly important for NXP, according to the company's CTO.

Elpida uses immersion litho for 50-nm process DDR3 SDRAM
The 50-nm process DDR3 SDRAM was developed using 193-nm immersion lithography technology and copper interconnect technology and has a chip size of less than 40-mm-squared.

Memory Test Platform Handles Multiple Device Types
Verigy’s newest memory test family handles flash, DRAM and multichip packages (MCPs) — at the price of a flash tester.

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Advantest Kyushu Systems Introduces ADS1911 Analog Test System (PR Newswire)
Source: biz.yahoo.com
Date: 1 hour 28 minutes ago
AMD 45nm roadmap details revealed
Source: www.techspot.com
Date: 2 hours 8 minutes ago
Semiconductors Not Rolling In Dough (at Forbes.com)
Source: www.forbes.com
Date: 2 hours 26 minutes ago
Brussels forum plans to lobby EU for chip industry support
Source: www.eetimes.eu
Date: 4 hours 24 minutes ago

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Wafer Processing SUSS MicroTec Names New CEO TSMC Begins Production of 40 nm Designs IBM Offers 45 nm SOI Foundry Solution View All Stories	Lithography SUSS MicroTec Names New CEO FSI Receives Repeat Polaris Order From GaAs Foundry Cymer Hitting Its EUV LPP Source Goals View All Stories
Yield Management TI Blitzes to Improve Fab Productivity ISMI Outlines 450 mm Wafer, NGF Roadmaps Despite Losses, Toshiba to Continue Aggressive Investments View All Stories	Inspection, Measurement & Test Measuring Material, Dopant Loss From Post-Implant Wafer Cleans ISMI Outlines 450 mm Wafer, NGF Roadmaps Photomask Printability, Standards and Cleaning Remain Concerns View All Stories
Clean Processing FSI Enters Single-Wafer Clean Market Measuring Material, Dopant Loss From Post-Implant Wafer Cleans Environmental Regulations Growing More Complex View All Stories	Materials December Sneak Peek: Optimize Wafer Thickness for 450 mm IBM Offers 45 nm SOI Foundry Solution Light on the Road to Low-k Integration View All Stories

News from Lexis Nexis

EV Group Introduces Tools for 3-D Interconnects

TEL and Novellus Collaborate on Copper Process Technology

China Sunergy Begins Construction of Shanghai Facility

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PERSPECTIVES FROM THE LEADING EDGE
Philip Garrou, Consultant,
November 29, 2008
Highlights of 3D ASIP
Without question the title of the RTI sponsored 3D Integration conference &ldqu...
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THE MEASURE OF ALL THINGS
Alexander E. Braun, Senior Editor, Semiconductor International
November 14, 2008
Hurray for the Do-Gooders!
We all know that technology has changed our lives, and as the innovators wh...
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VIEWS ON NEWS
David Lammers, News Editor, Semiconductor International
November 14, 2008
Luther Forest, Just in Time
As the Thanksgiving holiday approaches in the United States, people in the U.S. chip ...
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FLOAT ZONE
Laura Peters, Editor-in-Chief, Semiconductor International
September 26, 2008
Halla’s Perfect Storm of Technology Neglect
Back in 2005, I sat in on a great keynote speech by Brian Halla, CEO and President of...
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III-V dont switch off that good,because of relative low effective electron masses.In ...
student of physical engineering - 11/25/2008 7:14:20 AM PT
in response to Can We Afford High-k for III-Vs?

The CVD chamber can accomodate a piece of glass that is 2.2 m x 2.6 m, which results ...
Xprmntl - 11/20/2008 9:53:05 AM PT
in response to Applied's Solar Strategy Goes Very Large

There has been at least one earnest attempt to standardize 3D-ICs! Check out the IMIS...
Gretchen Patti - 11/19/2008 12:26:22 PM PT
in response to 3-D, TSV Need Standards and Thermal Solutions to Advance

Where the world is on memory requirements and progress, a 4MB MRAM device at 130nm te...
Shrikant Lohokare - 11/15/2008 5:13:57 PM PT
in response to Everspin Takes MRAM Up a Notch

» VIEW ALL TALKBACK THREADS

Metrology's Challenges at the Nanoscale Realm
Alain Diebold, CNSE

Professor Describes Unipolar CMOS Proposal
T.P Ma, Yale University

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