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May 23, 2008 |
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IN THIS EDITION
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NEWS |
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EDITOR'S PICKS |
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UPCOMING EVENTS |
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Dear Subscriber,
Several interesting findings came out of Chipworks' analysis of Intel's 45 nm Xeon processor, including details of the high-k/metal gate stack composition and a novel contact scheme. Despite all of the hubbub about 45 nm in the press, Chipworks has seen only (i.e., been able to access and analyze) two 45 nm parts, according to Dick James, senior technology analyst for the Ottawa-based teardown firm, indicating a delay in the roll-out of 45 nm technology. In other news, wafer bevel/edge processes are being delivered for improved yields, and we have full features this month on the use of copper interconnects in flash and DRAM chips, as well as a self-aligned barrier process that improves interconnect reliability. For more on wafer processing, check out our Wafer Processing Technology Channel:
www.semiconductor.net/wafer
Laura Peters, Editor-in-Chief
lpeters@reedbusiness.com
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Physical Analysis Provides Images of 45 nm
Laura Peters, Editor-in-Chief — Semiconductor International, 5/6/2008
From the different ways that strain is being implemented to the complexities of high-k/metal gate, the engineers at Chipworks Inc. (Ottawa, Canada) have uncovered many physical details of the 65 and 45 nm process technologies. Dick James, senior technology analyst for Chipworks, provided an overview of the firm's latest analyses at the recent Advanced Semiconductor Manufacturing Conference (ASMC) in Cambridge, Mass. Among these were two 45 nm chips: the Intel Xeon and Matsushita Electric Industrial Co. Ltd. UniPhier parts. More
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Applied Tackles Edge With Inflexion Polishing System
David Lammers, News Editor, and Laura Peters, Editor-in-Chief — Semiconductor International, 5/7/2008
Applied Materials Inc. (Santa Clara, Calif.) announced its entrance into the wafer edge cleaning sector, introducing the Inflexion system that performs edge polishing based on an abrasive tape approach. Semiconductor companies and their equipment suppliers are paying more attention to the wafer's edge, trying out various approaches to edge cleaning as the fast-moving liquids used in immersion lithography sweep residues out to the wafer's edge. More
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Splinter Sees Weak Order Period Looming for Equipment Vendors
David Lammers, News Editor — Semiconductor International, 5/13/2008
Applied Materials Inc.'s (Santa Clara, Calif.) CEO Michael Splinter said flash memory manufacturers have pushed out silicon equipment orders in the second half of this year, leading Applied to forecast a 40% reduction in its silicon equipment sales for the third fiscal quarter ending in July compared with its second fiscal quarter. More
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Novellus Offers Dry Strip Tools for HV Memory, Advanced Logic
David Lammers, News Editor — Semiconductor International, 5/19/2008
Novellus Systems Inc. (San Jose) announced two derivatives to its Gamma Express dry strip and clean platform: the G400, aimed at high-volume memory fabs, and the GxT, targeting the needs of advanced logic customers. The first G400 ashing system has shipped to a high-volume memory manufacturer in Asia, while the GxT system has been in production "for quite a while" at two foundries, said Kevin Jennings, general manager of Novellus' surface integrity group. More
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IBM Alliance Partners 'Open For Business' for 32 nm High-k/Metal Gate
David Lammers, News Editor — Semiconductor International, 4/14/2008
IBM Corp. (Armonk, N.Y.) and its partners are "open for business" for early customer design engagements using a bulk 32 nm technology with a high-k/metal gate stack, said Gary Patton, an IBM vice president. IBM announced that a low-power 32 nm design enablement package is now available, with a design prototyping shuttle starting in the third quarter of 2008 and continuing on a quarterly schedule. More
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ASM Simplifies High-k/Metal Gate Integration
Market Wire, 5/19/2008
ASM America Inc. announced the availability of a new atomic layer deposition (ALD) process implementing lanthanum oxide and aluminum oxide high-k cap layers that enable 32 nm generation high-k/metal gate stacks using a single metal, instead of the two different metals previously required for CMOS. High-k dielectrics integrated with metal gates enable faster and smaller chips ideally suited for high-performance servers and advanced products that require low power, such as laptops, PDAs and smart phones. More
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Mattson Ships Stripper to Taiwan Fab
PR Newswire, 5/8/2008
Mattson Technology Inc. announced the release of the Alpine system, the company's newest innovation targeted to meet the stringent requirements of advanced low-temperature photoresist strip processes on back-end-of-line (BEOL) and front-end-of-line (FEOL) applications for future technology nodes with a single tool. Alpine was developed to address the challenges of advanced low-k and other complex materials required to manufacture today's and future ICs. More
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Advanced Metallization Needs Integrate Copper Into Memory
Niranjan Kumar, Kevin Moraes, Murali Narasimhan and Prabu Gopalraja, Applied Materials Inc., Santa Clara, Calif. — Semiconductor International, 5/1/2008
Logic interconnect technology has been driven by dual-damascene feature scaling, low-k integration and copper interconnect reliability performance requirements. With memory devices going from aluminum to copper, requirements such as gap-fill extendibility are more challenging. More
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Self-Aligned Barrier Improves Interconnect Reliability
H.J. Wu, J. O'loughlin, R. Shaviv, M. Sriram, K. Chattopadhyay, Y. Yu, T. Mountsier, B. van Schravendijk, S. Varadarajan, G. Dixit and R. Havemann, Novellus Systems Inc., San Jose — Semiconductor International, 5/1/2008
A new PECVD self-aligned barrier using a germanium dopant offers a simple, cost-effective means of improving electromigration resistance of copper interconnects. More
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TSMC and the Reverse Temperature Effect
David Lammers, News Editor — Semiconductor International, 4/30/2008
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) recently held its annual technology symposium, with much of the attention on the foundry's 40 nm technology. TSMC would prefer that its leading-edge customers go directly from 65 to 40 nm design rules, making 40 nm much more than an afterthought 0.9× linear shrink. In fact, TSMC will skip 45 nm and only offer 40 nm for the general and processes, with 45 and 40 nm offerings for the low-power process that Qualcomm Inc. and others use. Blog
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| Webcast: Can Copper Deposition Break the 32 nm Barrier? |
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It is uncertain how extendible copper deposition processes will be at the 32 nm node and beyond. In this on demand webcast, a panel of industry experts discuss possible options and solutions for metallization schemes. Panelists include: Eric Eisenbraun of the University at Albany-SUNY, Zsolt Tökei of IMEC, and Daniel Josell of NIST.
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Automation Platform
Atlas is a standard automation platform that uses a well-estalished 200 and 300 mm-capable equipment front-end module (EFEM) to reliably align and transfer wafers from the loadports to the inspection station. Overall airflow and pressure balance between the process stage and EFEM has been optimized through computational flow dynamics modeling to ensure clean wafer transfer.
Owens Design Inc., Fremont, Calif.
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300 mm Wafer Probe Standard
The Elite 300 was designed to set a standard for extremely accurate and reliable 300 mm wafer probing for devices with process nodes at 45 nm and below.
Cascade Microtech Inc., Beaverton, Ore.
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June 1-4, 2008: IEEE International Interconnect Technology Conference
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June 2-4, 2008: International Conference on IC Design & Technology
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July 15-17, 2008: SEMICON West
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