 |
|
|
|
|
|
|
IN THIS EDITION
|
|
|
|
NEWS |
|
| |
|
|
|
EDITOR'S PICKS |
|
| |
|
|
|
PRODUCTS |
|
| |
|
|
|
UPCOMING EVENTS |
|
|
|
|
| |
|
|
|
|
Dear Subscriber,
In what could be one of those simple yet remarkable breakthroughs that may change the face of the semiconductor industry, scientists have discovered that processing wafers on (110)-oriented wafers, as opposed to the typical (100) orientation, enables a dramatic improvement in performance. It is well-known that PMOS transistors work best in (110) and NMOS in (100). A technique called hybrid-orientation technology (HOT) was developed by IBM in 2003 that combines both orientations on the same wafer through epitaxial silicon growth. It works great, but it's expensive. The problem with using just (110) alone, or so it was thought, was that PMOS was improved but NMOS was degraded. The new research (see first item below) shows that NMOS performance is not degraded but maintained. Mother Nature can indeed be kind. Remember that you can always find other useful information at our Wafer Processing Technology Channel:
www.semiconductor.net/wafer
Peter Singer, Editor-in-Chief
sieditor@aol.com
|
|
|
Advertisement
|
| Is Your Product Among the Best of the Best? |
 |
Don't miss your chance to be recognized with a 2008 Editors' Choice Best Product Award! Enter your product in the 19th annual awards, judged by Semiconductor International's editors, with winners recognized in SI's July issue, as well as a ceremony at SEMICON West. Entry deadline is March 31, 2008.
Get more information and download the entry form today!
|
|
|
|
|
|
|
|
|
|
|
|
CMOS on (110) Silicon May Have Cost Appeal
David Lammers, News Editor — Semiconductor International, 1/23/2008
Cost-sensitive consumer ICs may be well-served by CMOS on (110)-oriented silicon, although the question remains "to-be-decided," said Scott Thompson, a professor at the University of Florida (Gainesville, Fla.). Results have shown a 15% performance boost on ring oscillator tests, compared with standard (100) silicon. More
|
|
|
|
|
AMD Has Internal 45 nm Silicon; 45 nm Production Expected
David Lammers, News Editor — Semiconductor International, 1/17/2008
Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.) has "internal samples" of 45 nm silicon now, said Dirk Meyer, president and COO, putting the company on track to start ramping 45 nm microprocessor production in the first half of this year. More
|
|
|
|
|
Heterogeneous CMOS Gaining Momentum
David Lammers, News Editor — Semiconductor International, 1/10/2008
Research groups are stepping up efforts in heterogeneous semiconductors as a way of extending CMOS, using epitaxial techniques to deposit materials with higher mobilities than silicon. Heterogeneous devices may be formed on silicon wafers, incorporating, for example, germanium in the pFETs and III-V materials in the nFETs, including GaAs, InGaAs or InSb. More
|
|
|
|
|
Hutcheson: 2025 Likely Date for 450 mm
Alexander E. Braun, Senior Editor — Semiconductor International, 1/16/2008
The 450 mm wafer generation is unlikely to occur over the next dozen years, with 2025 as the "likely date" that the larger wafers will come into use, said Dan Hutcheson, CEO of market research firm VLSI Research Inc. (Santa Clara, Calif.). More
|
|
|
|
|
ISMI Publishes Guidelines for Equipment IP Protection
Staff — Semiconductor International, 1/15/2008
The International Sematech Manufacturing Initiative (ISMI, Austin, Texas) announced a set of guidelines for protecting intellectual property (IP) within process equipment. The goal is to embed IP protection in equipment software and create a secure framework for tools used by consortia and other collaborative R&D environments. More
|
|
|
|
|
Toshiba CEO Comments on SOI
Kenji Tsuda, Asia Contributing Editor — Semiconductor International, 1/9/2008
Toshiba Corp. (Tokyo) may modify the Cell processor to Toshiba's bulk CMOS process, moving away from the silicon on insulator (SOI) process, said Atsutoshi Nishida, Toshiba president and CEO. More
|
|
|
|
|
MIRAI Team Studies Threshold Voltage Variation Causes
Kenji Tsuda, Asia Contributing Editor — Semiconductor International, 1/7/2008
With transistor threshold voltage variability now a top-shelf concern, a group of researchers led by Toshiro Hiramoto at Japan's Millennium Research for Advanced Information (MIRAI, Tokyo) consortium have studied the role of dopant levels and other factors. More
|
|
|
Advertisement
|
| Check Out SI’s Technology Library |
 |
Discover 100s of pages of technical content from key suppliers in the industry.
- White Papers
- Research
- Spec Sheets
- Product Information
- And much more
www.semiconductor.net/techlibrary |
|
|
|
|
|
|
|
|
|
|
|
|
32 nm Marked by Litho, Transistor Changes
Laura Peters, Lead Technical Editor — Semiconductor International, 1/1/2008
The transition from 45 to 32 nm is likely to involve some key material changes and a major change in lithography to double patterning for critical layers. Selections will be driven by costs and specific product needs. More
|
|
|
|
|
Sustainable Chamber Cleaning Solutions
Peter Lai and Paul Stockman, Linde Electronics, Murray Hill, N.J.; Greg Shuttleworth, Linde Electronics, Thornton Cleveleys, UK — Semiconductor International, 1/1/2008
Sustainable and production-proven chamber cleaning solutions allow device manufacturers to deliver increased productivity and reduce environmental impact while "taking out the trash." More
|
|
|
|
|
Webcast: Highlights of the 2007 ITRS
Moderated by Laura Peters, Lead Technical Editor — Semiconductor International, 1/22/2008
Originally broadcast earlier this week and now available to view on demand, this hour-long webcast is moderated by Lead Technical Editor Laura Peters, with a panel discussion on the various ramifications of the latest updates to the International Technology Roadmap for Semiconductors (ITRS). Alan Allan, an Intel external programs staff engineer and member of the ITRS International Roadmap Committee (IRC), leads the explanation of the changes, with eight leaders of the technical working groups (TWGs) joining the discussion. View
|
|
|
Advertisement
|
| Feb. 19: Preparing for High-Volume Immersion Lithography |
 |
Broadcast in both English and Japanese, this webcast will look at the most pressing challenges facing immersion lithography and the solutions that are being worked on. Panelists include: Soichi Inoue, Toshiba Semiconductor Co.; Burn Lin, TSMC; Kurt Ronse, IMEC; Bryan Rice, Sematech.
Register Now!
Sponsored by: ASML |
|
|
|
|
|
|
|
|
|
|
|
Wafer Pre-Alignment
In-Sight 1820 is a vision-based wafer pre-aligner. It uses the company's NotchMax alignment technology to provide precise non-contact measurement of wafer position and orientation.
Cognex Corp., Natick, Mass.
More
|
|
|
|
|
CMP Endpoint System
The FullVision system enables real-time control of dielectric CMP processes to the 45 nm device node and beyond. The system combines the company's patented window-in-pad technology with multiple-wavelength spectroscopy to deliver advanced in situ endpoint capability for a variety of dielectric materials.
Applied Materials Inc., Santa Clara, Calif.
More
|
|
|
|
|
Bevel Cleaning System
The Coronus is a plasma-based bevel cleaning system designed to reduce yield loss caused by defects that originate near the wafer's edge. The system combines the multiple material cleaning capability of plasma with a confinement technology that protects the die area.
Lam Research Corp., Fremont, Calif.
More
|
|
|
|
|
|
|
Jan. 30-Feb. 1, 2008: SEMICON Korea 2008
|
|
Feb. 24-29, 2008: SPIE Advanced Lithography
|
|
March 18-20, 2008: SEMICON China 2008
|
|
|
|
|
Advertisement
 |
|
SUBSCRIBE
To activate a new FREE
e-mail subscription, visit
Click Here
CHANGE YOUR PROFILE
To change delivery
options, e-mail address or
register for other
newsletters, Click Here.
QUESTIONS?
If you have any questions
or need further assistance,
please contact our Online
Support Team.
Online Support Team
Reed Business Information
2000 Clearwater Drive
Oak Brook, IL 60523
Fax: 630-288-8394
You are receiving this
e-mail because you have
either requested a
newsletter or a magazine
from Reed Business
Information.
Privacy Policy
** If you found this FREE
newsletter valuable, please
email it to a colleague!
To request your FREE
magazine subscription to
Semiconductor International, Click Here. |
|
|
|
|
