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| Focus on: 3-D Interconnects February 27, 2009 |
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Dear Subscriber,
Going vertical -- connecting two or more die with vertical through-silicon vias (TSVs) -- is slowly going from R&D to real volumes, starting with CMOS image sensors. If TSVs succeed in connecting logic and memory chips, or provide fast interconnections among memory slices, then huge volumes will be achieved. The technology could give the entire chip industry a means of scaling cost and performance at a time when traditional shrinks are harder to come by. As a result, companies such as IBM, Samsung Electronics and Toshiba are actively pursuing 3-D products. One expert, IEEE fellow Phil Garrou, provides weekly blogs on this important trend. Phil's blog, regular stories and press releases, can be found on the Packaging Channel of Semiconductor.net. www.semiconductor.net/packaging
David Lammers, News Editor
David.lammers@reedbusiness.com
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| This Week's Top Stories... |
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Most Viewed Articles for the Week of SPIE Advanced Lithography conference, held in San Jose over the past five days, prompted Intel's Director of Lithography to go public with concerns about the EUV mask infrastructure. Plenary speakers took the SPIE podium with their own views of lithography's future. Those stories complemented several others in our Top 5 this week about troubles on the memory chip front, including the dire situations at Qimonda and Spansion and a 200 mm specialty DRAM fab closure by Micron Technology.
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Perspectives From the Leading Edge: 3-D IC at the 2009 ISSCC Continued
Philip Garrou, Contributing Editor -- Semiconductor International, 2/25/2009
At ISSCC, the University of Tokyo and Toshiba jointly presented a 3-D integrated solid-state drive (SSD) that addresses what they called the key design issue for SSD development -- decreasing power consumption. The solution was a stack of NAND flash chips, DRAM, a NAND controller and a new low-power voltage generator. More
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Eclipse PVD Tool Handles Thinned Wafers
David Lammers, News Editor -- Semiconductor International, 2/26/2009
The OEM Group (Phoenix) said it will soon ship an MRC Eclipse physical vapor deposition (PVD) tool that can handle very thin, 125 micron wafers used in 3-D through-silicon via (TSV) applications. The PVD system is equipped with a front end that includes thin wafer-handling capabilities developed by Mechatronic Systemtechnik GmbH (Villach, Austria). More
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Applied Materials Joins EMC-3D Consortium
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 2/24/2009
Applied Materials is now a member of EMC-3D, the international semiconductor equipment and materials alliance that is working to develop cost-effective TSV technology. The consortium targets cost-effective and manufacturable through-silicon via (TSV) process flows for 3-D chip stacks and MEMS integration. More
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Podcast: The Package as System-Level Solution
Alexander E. Braun, Senior Editor -- Semiconductor International, 2/1/2009
Mahadevan "Devan" Iyer, director of packaging at Texas Instruments, has more than 25 years of experience in microelectronics and packaging. He discussed advanced packaging issues with Senior Editor Alexander Braun. More
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Perspectives From the Leading Edge: 3-D IC Integration at the 2009 IEEE ISSCC
Philip Garrou, Contributing Editor -- Semiconductor International, 2/20/2009
At the International Solid State Circuits Conference (ISSCC), 3-D related papers included presentations by NEC Electronics and Infineon Technologies. NEC detailed their vias-first approach to 3-D integration, which they call "chip-stacked flexible memory." Werner Weber of Infineon indicated 3-D TSVs are being examined for use in tire pressure monitoring sensor devices. More
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ASE Leads Gartner Packaging Market Share Ranking
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 2/25/2009
Two packaging companies can boast revenue >$2B: ASE and Amkor. They're followed by SPIL and STATS ChipPAC in the >$1B category, and the remaining six companies' revenues range from ~$250M to $900M. The Top 10 companies' combined revenue totaled $12.5B in 2008. Gartner analyst Jim Walker said the top companies appear to all be focusing in varying degrees on wafer-level packaging (WLP) and through-silicon vias (TSVs), while driving down costs. More
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Léti and Brewer Science Collaborate on 3-D, MEMS
Staff -- Semiconductor International, 2/23/2009
Léti and Brewer Science said they will strengthen their research collaboration on materials used in 3-D and MEMS manufacturing, including temporary bonding adhesives. The R&D groups will work together for three years in a common laboratory focused on ultrathin wafer processing flows for 3-D packaging. More
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Perspectives From the Leading Edge: Tezzaron Announces 3-D IC Multi Project Wafer Program
Philip Garrou, Contributing Editor -- Semiconductor International, 2/2/2009
For companies interested in building prototype 3-D IC logic devices, Tezzaron has just announced a multi-project wafer program. Up to ten participants will design two-layer logic devices to be built and bonded on the shared program wafers. Both the logic stack and the DRAM integration will use high-density interconnect in order to examine global I/O and memory bandwidth capabilities in 3-D ICs. More
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Besi, TNO Develop a Die Bonder for 3-D Chip Stacking
Gail Flower, Contributing Editor -- Electronic News, 2/10/2009
TNO and BE Semiconductor Industries NV (Besi) are developing a production die bonder for the 3-D chip stacking market, with the first prototype expected to be ready by the second half of the year. There is no equipment on the market for die bonding several stacked chips in a production environment at present, said Roger Görtzen, a developer at TNO. More
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AMEC Plans DRIE for 3-D Interconnects
David Lammers, News Editor -- Semiconductor International, 2/9/2009
Advanced Micro-Fabrication Equipment Inc. (AMEC, Singapore) will extend its etch product portfolio into the deep reactive ion etch (DRIE) systems required for 3-D interconnects, said AMEC CEO Gerald Yin. "Our key customers are very aggressive about 3-D devices with through-silicon vias," Yin said. "We want to adapt our technology to etching the deep trenches. I see through-silicon etching happening for us this year or next." More
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Alchimer to Launch AquiVia Process for TSVs Midyear
Gail Flower, Contributing Editor -- Electronic News, 2/6/2009
Alchimer SA this summer will launch its third product: AquiVia, a process used for wet deposition of the insulation and barrier layers inside high-aspect ratio through-silicon vias (TSVs). AquiVia eliminates dry process techniques from TSV metallization, according to the start-up company. Using AquiVia, conformal, uniform insulation and barrier layers can be produced inside a TSV with aspect ratios at 10:1, even on the highly scalloped TSV etch profiles produced by the DRIE/Bosch process, the company said. More
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Ziptronix to License 3-D Bonding Technologies
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 2/3/2009
Ziptronix Inc. is preparing licensing strategies for its low-temperature covalent bonding and Direct Bond Interconnect technologies that enable wafer-to-wafer or chip-to-wafer bonding -- without the need for high-temperature compression techniques that can cause yield issues and send processing costs soaring. More
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IITC Set for Sapporo in June, Europe in 2011
Staff -- Semiconductor International, 1/8/2009
The International Interconnect Technology Conference (IITC) will move from its traditional venue near the San Francisco airport to Sapporo, Japan, in early June. The conference will focus on 3-D technologies, packaging and system integration, novel materials and interconnect systems, and environmental issues, among others. More
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