 |
|
| Focus on: 3-D Interconnects December 5, 2008 |
 |
|
|
|
|
|
|
Dear Subscriber,
Attending the recent 3-D Architectures for Semiconductor Integration and Packaging conference, Senior Editor Alex Braun and Consultant/Blogger Phil Garrou spun their spotlights on the technology, looking for what it will take to make it a reality. Garrou, an IEEE fellow for his packaging contributions over the decades, counseled patience and downplayed the more hyperbolic forecasts for adoption of through-silicon vias (TSVs). We've got lots of 3-D angles for you here from Garrou, Braun and others, with continuing coverage on our Packaging Technology Channel:
www.semiconductor.net/packaging
David Lammers, News Editor
david.lammers@reedbusiness.com
|
|
|
|
ADVERTISEMENT
| Webcast: 2009 Semiconductor Industry Forecast |
 |
In this Dec. 18 webcast, leading analysts throughout the semiconductor and electronics industries will provide their forecasts of the 2009 market, what factors will most impact capital spending by device manufacturers worldwide and how quickly economic turnaround might begin to materialize.
Register now!
Sponsored by: SAP
|
|
|
|
|
| This Week's Top Stories... |
|
|
Most Viewed Articles for the Week of December 1, 2008
Qimonda indicated that it may have found a partner that would bail it out of its tight financial spot. A blog by Editor-in-Chief Laura Peters about job opportunities in the solar industry attracted attention. Applied Materials announced a new TSV etch tool, and Novellus and TEL announced that they have collaborated on a new copper deposition process. In these tight times, companies are still investing: China Sunergy broke ground on a solar cell factory.
|
|
|
ADVERTISEMENT
| Free Subscription to Semiconductor International |
 |
Semiconductor International is the leading technical publication covering the global semiconductor industry. It provides focus on the latest research projects, new technology developments and much more!
Subscribe Now!
|
|
|
|
|
|
|
|
|
|
3-D, TSV Need Standards and Thermal Solutions to Advance
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/19/2008
At the 3-D Architectures for Semiconductor Integration and Packaging conference, Michael Shapiro, 3-D chief technologist of IBM's Systems and Technologies Group, outlined four drivers important to 3-D development, the first being bandwidth. More
|
|
|
EV Group Introduces Tools for 3-D Interconnects
PR Newswire, 12/1/2008
EV Group introduced the NT suite of mask aligners, wafer-to-wafer (W2W) bond aligners and measurement systems to address increased demand for higher-precision alignment accuracy. More
|
|
|
Perspectives From the Leading Edge: Best of the Rest at 3-D ASIP
Philip Garrou, Consultant -- Semiconductor International, 12/4/2008
Phil Garrou blogs that Jan Vardaman of TechSearch International is sticking by her conservative predictions for 3-D IC adoption, with DRAM not happening until after 2010 and NAND after that. Jeff Perkins said Yole Developpement is standing by its aggressive adoption curve for 3-D IC in general and especially for memory. More
|
|
|
ADVERTISEMENT
| Webcast: Metrology Gears for the Nanotech Age |
 |
The resolution, accuracy and capability of many metrology technologies are reaching their limits, and may not meet all the needs of nanotech manufacturing processes. In this on demand webcast, possible metrology technology options are discussed by experts in the field.
View now!
|
|
|
|
|
|
|
3-D Integration Lacking in Design and Test Support
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/18/2008
Leading 3-D consultant Philip Garrou said the Holy Grail of 3-D is heterogeneous integration, where the aim is to bond disparate technologies and functionalities. A significant problem is test. "When stacking up functions, stacking a good die with a bad die can catastrophically affect results," Garrou said at a symposium leading up to the 3-D Architectures for Semiconductor Integration and Packaging conference. More
|
|
|
Perspectives From the Leading Edge: Highlights of 3-D ASIP
Philip Garrou, Consultant -- Semiconductor International, 11/29/2008
Phil Garrou summarizes key points from the 3-D Architectures for Semiconductor Integration and Packaging conference, including the keynote presentations by IBM, Intel, Micron and ASE. A Micron manager outlined the cost structure of 3-D ICs for DRAMs, and said a via-first process flow with copper-filled vias appears to be the way to go. More
|
|
|
3-D Integration Development Threatened by Economic Uncertainty
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/17/2008
Confidence in 3-D integration's future is mixed with concern about survival in the current economy. "We all know that the qualification of both processes and products each take about a year-and-a-half to two years," said 3-D expert Phil Garrou. "I always get heartburn when some of the marketeers try to tell us that this is going to happen by 2010 -- we know that this is impossible because nothing is being done yet in the way of orders." More
|
|
|
ADVERTISEMENT
| RSS Feeds – Bring The Headlines To You |
 |
Subscribe to SI's RSS Feeds to automatically receive the latest news headlines, technical features, blog postings, etc. as soon as they are posted. The power of RSS lies in its ability to bring all of the news and content that interests you into one place.
Subscribe now!
|
|
|
|
|
|
|
TMV: An 'Enabling' Technology for Next-Gen PoP Requirements
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 11/4/2008
Amkor Technology Inc. has developed a forward-looking matrix mold laser ablation process to create through-mold via (TMV) solderable interconnects. TMV bottom packages use matrix strip molding. After molding, a laser process ablates the mold compound in the locations where TMV interconnects are required. More
|
|
|
Interposers Play a Key Role in 3-D ICs
Kenji Tsuda, Asia Contributing Editor -- Semiconductor International, 10/15/2008
Participants at the Jisso Forum 2008 emphasized the important role that interposers will continue to play as 3-D interconnects using through-silicon vias (TSVs) become more prominent. A Renesas study compared package thicknesses of a conventional flip-chip and an interposer-enabled memory-logic 3-D stack. More
|
|
|
IMEC Views 3-D Stacking as System Design
Laura Peters, Editor-in-Chief -- Semiconductor International, 10/14/2008
IMEC managers said the research center has made significant progress creating test 3-D ICs, using die-to-die stacking. IMEC's Eric Beyne said achieving coplanar and particle-free surfaces still presents processing challenges. He described the dual-damascene via processing as comparable to traditional front-end interconnect via processing, but with larger features. More
|
|
|
Perspectives From the Leading Edge: You Can't Always Get What You Want...
Philip Garrou, Consultant -- Semiconductor International, 11/24/2008
Consultant and blogger Phil Garrou notes it takes patience to develop a new technology such as 3-D interconnects. "We are doing this because it leads us to repartitioning of chips so we can stack functions being built by optimized processes (the opposite of SoC -- system-on-chip solutions)," Garrou writes. More
|
|
|
Rudolph NSX Selected for Inspection of TSV Process
Staff -- Semiconductor International, 12/3/2008
Rudolph Technologies Inc. said that it has installed an NSX 115 Macro Inspection System at a major European fab. The NSX tool performs 2-D and 3-D metrology and inspection of defects during the same production cycle. More
|
|
|
Applied Offers TSV Etcher, In-Fab Mask Inspection
David Lammers, News Editor -- Semiconductor International, 12/1/2008
Applied Materials Inc. announced its Silvia deep silicon etcher for creation of the smooth sidewalls required for 3-D interconnects. Ellie Yieh, general manager of the etch and cleans business unit, said multiple via etch steps represent a large portion of the cost of creating TSV 3-D interconnects. More
|
|
|
NEXX Licenses Alchimer's Coating Technology
Laura Peters, Editor-in-Chief -- Semiconductor International, 10/8/2008
Alchimer SA (Paris) said it has licensed its eG ViaCoat product for creating conformal copper seed layers for through-silicon via (TSV) applications to NEXX Systems Inc. (Billerica, Mass.), a maker of electroplating tools. The partnership allows the combination of 300 mm tooling with the optimized chemistry and recipes used in the eG ViaCoat for copper seed deposition. More
|
|
|
Perspectives From the Leading Edge: TSMC Roadmap, DRAM Timing and Sematech Highlights
Philip Garrou, Consultant -- Semiconductor International, 10/27/2008
Phil Garrou blogs on TSMC "IT17" vias first technology, which they indicate would initially be made available on 17 micron pitch. "TSMC is still looking at vias first options and deciding on the best way to go. Since the technology decision has not been made yet, I would not be surprised to see this pushed back to 2012," Garrou writes. More
|
|
|
|
ADVERTISEMENTS
 
|
|
| |
|
|
|
CHANGE YOUR PROFILE To change delivery options, e-mail address or
register for other newsletters, Click Here.
QUESTIONS? If you have any questions or need further assistance, please contact our Online Support Team.
Online Support Team
Reed Business Information
2000 Clearwater Drive
Oak Brook, IL 60523
|
Privacy Policy
** If you found this FREE newsletter valuable, please email it to a colleague!
To request your FREE magazine subscription to
Semiconductor International, Click Here
To activate a new FREE e-mail subscription, Click Here |
|
|
|
|
|
