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November 19, 2008 |
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IN THIS EDITION
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NEWS |
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EDITOR'S PICKS |
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PRODUCTS |
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UPCOMING EVENTS |
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Dear Subscriber,
Covering 3-D integration at a symposium and conference this week, Senior Editor Alexander Braun landed two articles under the "Editor's Picks," as must-reads. He provides details about the challenges facing 3-D integration (which include test, yield and design), and also describes the impact the current economic "uncertainty" is having on 3-D integration development. To keep up with more in 3-D integration and other packaging fronts, check back regularly at our Packaging Technology Channel:
www.semiconductor.net/packaging
Sally Cole Johnson, Contributing Editor
scolejohnson@mac.com
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Advanced Fine-Pitch Packaging Development at 65 nm in Singapore
Business Wire, 11/17/2008
Singapore's Institute of Microelectronics (IME) and Chartered Semiconductor Manufacturing have successfully optimized a range of fine-pitch packaging technologies for copper metallization and low-k dielectric silicon processes at 65 nm and below. The Chartered-IME collaboration has led to a greater understanding of chip-package interaction of low-k devices through modeling, simulations and reliability verifications on silicon. More
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IMEC and Panasonic Sign Research Contract
Business Wire, 11/12/2008
IMEC and Panasonic signed a joint research contract covering most of the research domains of IMEC. More
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SUSS MicroTec Introduces iVista Failure Analysis Tool
Business Wire, 11/11/2008
SUSS MicroTec Test Systems announced the iVista LC digital microscope capable of delivering high-resolution digital images in conjunction with laser-cutting capabilities. More
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Semitool Full-Year Revenues Increase 11%
Marketwire, 11/11/2008
Semitool Inc. reported financial results for its fourth quarter and full fiscal year ended Sept. 30, 2008. Fourth quarter revenue increased 27% to $60.1M from $47.2M in last year's fourth quarter. More
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Patent Award: Interposer Substrate
US Fed News, 11/14/2008
Researchers at Renesas Technology Corp. (Tokyo) have developed an interposer substrate manufacturing method that provides a "method for forming a narrow-pitch flip-chip bonding electrode and a wire bonding electrode at the same time so as to reduce cost of a substrate." More
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Tessera Licenses Shellcase MVP Technology to Qtech
Business Wire, 11/11/2008
Tessera Technologies Inc. said Q Technology has licensed Tessera's image sensor packaging technology. More
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Amkor Licenses FusionQuad Packaging Technology to ASAT
Business Wire, 11/7/2008
Amkor Technology Inc. said ASAT Holdings Ltd. has entered into an agreement to license Amkor's FusionQuad package technology. More
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Tessera Signs Agreement With Motorola
Business Wire, 11/10/2008
Tessera Technologies Inc. announced that Motorola Inc. has signed an agreement with Tessera for an option to license Tessera's chip-scale packaging (CSP) technology. More
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3-D Integration Development Threatened by Economic Uncertainty
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/17/2008
As presenters and attendees prepared for the opening of this year's 3-D Architectures for Semiconductor Integration and Packaging conference, confidence in the technology's future was mixed with concern about survival in the current economy. More
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3-D Integration Lacking in Design and Test Support
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/18/2008
At a recent symposium on 3-D integration, leading expert Philip Garrou detailed the rise of the technology as well as the challenges facing it, including test, yield and design. More
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Planar Air-Bearing Motion Platform
The PlanarHD "high dynamic" air-bearing motion platform has been designed specifically to maximize throughput by providing up to 2 m/sec scan velocity and 2.5 g acceleration. The design uses a highly engineered mechanical structure that increases air-bearing stiffness and decreases moving mass. Aerotech Inc., Pittsburgh More
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Dec. 1-2, 2008: Ninth VLSI Packaging Workshop
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Dec. 9-12, 2008: EPTC 2008
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Dec. 10-12, 2008: Electrical Design of Advanced Packaging & Systems
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