Date: Oct. 13-15, 2008

Location: Santa Clara, Calif.

The relentless drive in the semiconductor industry for smaller, faster and cheaper ICs has brought the industry to the 45 nm technology node. The speed, computational power and enhanced functionality of ICs based on this advanced technology promise to transform both our work and leisure environments. However, the implementation of this technology has opened a Pandora’s box of manufacturing issues as well as set the stage for a range of manufacturing challenges that require revolutionary new process methodologies as well as innovative, new equipment for the 32 and 22 nm nodes. This seminar addresses all of these manufacturing issues with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 45 nm node technology, as well as previews the upcoming manufacturing issues of the 32/22 nm nodes.

The central theme of this seminar is an in-depth presentation of the key 45/32/22 nm node technical issues: CD control, electrical leakage mitigation, high-k/metal gate integration, ultrashallow junction implementation, immersion lithography, mobility enhancement, copper/low-k integration, and other critical processing problems. Each section of the course will present the relevant technical issues in a clear and comprehensible fashion, as well as discuss the proposed range of solutions and equipment requirements necessary to resolve each issue.

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