Date: July 15, 2008

Location: The AMD Commons Bldg, Sunnyvale, Calif.

Latch-up continues to be of interest today in advanced CMOS, mixed-signal CMOS, RF, CMOS, BiCMOS and BiCMOS SiGe. The latch-up tutorial will provide a discussion on device-level latch-up physics, latch-up metric and design criteria, latch-up test structures, test methods, latch-up measurement techniques, device-level AZD simulation, and new latch-up issues. Both internal and external latch-up phenomena, as well as DC and transient latch-up will be addressed. Latch-up structures, guard ring physics, and characterization will be discussed in depth. The tutorial will provide examples of discussion on latch-up device-level simulation using latch-up scaling issues as examples. Latch-up process solutions, such as heavily doped buried layers (HDBL) and triple wells will be shown. The tutorial will briefly discuss latch-up standards. The tutorial will end with a discussion on the state-of-the-art latch-up issues and characterization techniques and tools.

www.esda.org/education.html