3-D Integration Lacking in Design and Test Support
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/18/2008

At a symposium held at the 3-D Architectures for Semiconductor Integration and Packaging conference, expert Philip Garrou detailed how 3-D architecture and through-silicon vias (TSVs) have become a requisite to enable the continuation of the progress experienced so far for decades to come, because Moore's Law is headed toward a red brick wall, with shrinks fundamentally limited by physics within the next 10 or so years. However, there is a critical lack of EDA and test resources. More

3-D, TSV Need Standards and Thermal Solutions to Advance
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/19/2008

At the 3-D Architectures for Semiconductor Integration and Packaging conference, different sessions converged on the conclusion that although 3-D and TSV technologies are progressing and coming into use, there still are unanswered questions about practical, real-world, high-level applications. Among these is a lack of standards and metrology to enable all sectors of the industry -- OEMs, material providers, designers and fabs -- to work efficiently together. More

Zeiss Sets Microscopy Resolution Record Using Scanning Helium Ions
Business Wire, 11/21/2008

Carl Zeiss SMT has set a new record resolution benchmark for scanning electron and ion microscopy, pushing scanning beam technologies beyond its current limits. Using its Orion helium-ion microscope, a surface resolution of 0.24 nm has repeatedly been achieved (25-75% edge-rise criterion) on various samples. This resolution -- which is close to the diameter of a single atom -- is 3x better than even the most sophisticated scanning electron microscopes are able to achieve today with the same surface sensitivity. More

FormFactor Doubles DRAM Test Capacity
Marketwire, 11/11/2008

FormFactor Inc. introduced DC-Boost, an advanced test technology to increase probe test capacity. The new wafer probe card capability enables more efficient use of tester channels on test equipment, doubling the number of devices that can be tested simultaneously, and significantly increasing test cell throughput on new test equipment. More

CyberOptics Names Ferris Chen Director of Asian Sales
Marketwire, 11/11/2008

CyberOptics Semiconductor Inc., which manufactures wireless metrology devices for wafer processing equipment, has named Ferris Chen, a veteran of Asia's semiconductor industry, its director of Asian sales to manage growth of the company's WaferSense brand in the region and implementations at fabs in Taiwan, China, Singapore and Malaysia. More

Test Leaders Unite Behind Alliance for Improved Productivity
Market Wire, 10/28/2008

Semiconductor and test community leaders have formed a new organization to foster pre-competitive collaboration and standards development to improve semiconductor industry productivity. The Collaborative Alliance for Semiconductor Test (CAST) seeks broad industry participation to resolve common issues that will ultimately lead to higher equipment utilization, greater return on investment for equipment users, and lower redundant R&D costs in non-differentiating product areas for test equipment providers. More

ISMI Outlines 450 mm Wafer, NGF Roadmaps
David Lammers, News Editor -- Semiconductor International, 10/27/2008

ISMI managers described progress at the 450 mm wafer Interoperability Test Bed, and described the Phase 2 roadmap at last month's ISMI Symposium on Manufacturing Effectiveness. ISMI members funded the Factory Integration Interoperability Test Bed (ITB), aimed at developing standards for wafer handling, wafer carrier and metrology vendors. ISMI's test bed plans to create a wafer bank of single-crystal silicon wafers, and work with metrology vendors to develop inspection tools for particle detection, geometry tools and others. More

Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
N. Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Y.S. Tan, Chartered Semiconductor Mfg. Ltd., Singapore; T. Tillery, S. Savas, A. Kadavanich and A. Wiesnoski, Mattson Technology, Fremont, Calif. -- Semiconductor International, 11/1/2008

Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasing number of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method is described, which provides accurate relative measurements of amorphized silicon or SiGe loss caused by different strip/clean processes. More

Racing to Excellence in PV Manufacturing
Bettina Weiss, SEMI -- Semiconductor International, 11/1/2008

SEMI's PV Group companies are pursuing collective goals, including long-term growth, sustained profitability and industry development, and global reach in the area of standards. The PV industry lacks global specifications and test methods to help reduce cost and accelerate time to market. Through the SEMI International Standards Program, experts leverage existing SEMI standards and safety guidelines and identify areas in the manufacturing process truly unique to PV that must be better understood, investigated and resolved on a global basis, with support from the supplier and customer communities. More

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