It's an exciting month for sub-45 nm production: Intel and Micron announced on Monday that they are entering mass production of 34 nm NAND flash devices with their joint venture, while TSMC rolled out 40 nm designs for several of its customers. It seems that despite the laws of physics and the high cost of technology progression, the leading device makers always find a way to make it happen. And speaking of making it happen, 450 mm wafer testing and standardization are progressing despite far-ranging uncertainty on the topic. We also have a sneak peek at a 450 mm article that will run in our December print issue -- it closely examines the selection of wafer thickness based on a range of factors including wafer sag, slip and yields. Catch up with the latest advances here, and keep up to date on our Wafer Processing Technology Channel:

Laura Peters, Editor-in-Chief
lpeters@reedbusiness.com

Intel, Micron Move Into Mass Production With 34 nm NAND Flash
Business Wire, 11/24/2008

Intel Corp. and Micron Technology Inc. announced mass production of their jointly developed 34 nm, 32 Gb multi-level cell (MLC) NAND flash memory device. More

TSMC Begins Production of 40 nm Designs
David Lammers, News Editor -- Semiconductor International, 11/17/2008

TSMC said it is now in production of 40 nm designs for a wide variety of customers, ranging from Altera to Sun Microsystems. Although Qualcomm and others have used a TSMC 45 nm process, TSMC Vice President Di Ma said the company developed an IP platform and design support ecosystem for the 40 nm design rules. More

ISMI Outlines 450 mm Wafer, NGF Roadmaps
David Lammers, News Editor -- Semiconductor International, 10/27/2008

ISMI managers described progress at the 450 mm wafer Interoperability Test Bed, and described the Phase 2 roadmap at last month's ISMI Symposium on Manufacturing Effectiveness. Also, the Next Generation Factory program at ISMI is continuing work on cycle time improvements for existing and greenfield 300 mm wafer fabs, including support for 12-wafer lots. More

Logic Technologies Face Off at IEDM
David Lammers, News Editor -- Semiconductor International, 10/28/2008

At the International Electron Devices Meeting (IEDM), coming up Dec. 15-17 in San Francisco, IBM and its partners AMD and Freescale will present a thin SOI technology used to create a 22 nm functional SRAM with a cell size of 0.1 um2. Intel researchers will detail their 32 nm logic platform, which delivers drive currents of 1.55 mA/um for the NMOS and 1.21 mA/um for the PMOS transistors. More

IBM Offers 45 nm SOI Foundry Solution
David Lammers, News Editor -- Semiconductor International, 11/10/2008

IBM is offering a 45 nm SOI foundry solution to customers seeking to reduce active power consumption. ARM developed an SOI standard cell library, in conjunction with SOI wafer vendor Soitec, that eases SOI designs. Chartered will provide a second-source foundry capability for high-volume SOI customers. More

SMIC Receives U.S. Licenses for 32 nm Production
Suzanne Deffree, Managing Editor, News -- Electronic News, 10/27/2008

As early as Jan. 1, the foundry can launch 32 nm logic process development in all of its own manufacturing facilities and can start 32 nm flash R&D in its 300 mm fab in Wuhan, China. More