Most Viewed Articles for the Week of November 17, 2008

With Senior Editor Alex Braun attending the 3-D Architectures for Semiconductor Integration and Packaging conference this week in Burlingame, Calif., the topic figures prominently in our Top 5 this week. But the buzz about 3-D integration wasn't enough to completely quell the interest in knowing more about recent layoffs and growing economic concerns -- or especially about continuing progress through technology generations at TSMC. More

Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif. -- Semiconductor International, 11/1/2008

Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasing number of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes. More

Resist Removal Walks a Tightrope
Ruth DeJule, Contributing Editor -- Semiconductor International, 8/1/2008

Between limiting damage to low-k materials and silicon removal at the gate, while definitely clearing away all photoresist and its residues, resist removal processes -- wet and dry -- continue to strive to maintain the right balance. More

Increasing Demands Require New Look at Wafer Cleans
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 8/1/2008

Smaller, more fragile structures, as well as a whole host of new materials will require a new look at cleaning solutions, with more need to combine approaches -- wet and dry, mechanical and chemical. More

IMEC Has Air Gaps in Post-22 nm Roadmap for Interconnects
Laura Peters, Editor-in-Chief -- Semiconductor International, 10/21/2008

Though copper will clearly remain the interconnect material of choice, there may be some material changes in the barriers and capping layers after the 22 nm node, said Rudi Cartuyvels, director of interconnect, packaging and system integration, at IMEC's annual research review meeting. To achieve k<2.0, air gaps must be employed. More

Trends in Shallow Junction Engineering
Ruth DeJule, Contributing Editor -- Semiconductor International, 4/1/2008

Chipmakers and equipment manufacturers alike are developing new techniques and integrating processes to meet stringent ITRS requirements for shallower junction depths. More

Self-Aligned Double Patterning Gains NAND Flash Favor
Chris Bencher, Applied Materials Inc., Santa Clara, Calif. -- Semiconductor International, 9/1/2008

Whether you call it frequency doubling, pitch reduction, spacer mask patterning or SADP, sidewall spacer transfer patterning techniques are being adopted at an accelerating rate by NAND flash device makers. This article describes the generic process flows and demonstrated capabilities of the technique. More

FSI Enters Single-Wafer Clean Market
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 11/3/2008

FSI International (Chaska, Minn.) has made its single-wafer debut with its Orion cleaning system, which enables advanced wafer cleaning capabilities for such critical device structures as ultrashallow junctions, high-k/metal gates and metal capping layers. Innovative spray-bar and closed-chamber designs improve on competing single-wafer platforms, according to FSI's Scott Becker. More

Ulvac Intros High-Throughput Asher
Laura Peters, Editor-in-Chief -- Semiconductor International, 7/16/2008

At SEMICON West, Ulvac introduced the Enviro Optima resist strip and residue cleaning system, which delivers 400 wph, with a modest 300 mm footprint and at the cost of $1.3M. More