Perspectives From the Leading Edge: 3-D IC at the WLP Conference
3-D integration has now penetrated the Wafer Level Packaging Conference, which SMTA holds each fall in San Jose, notes Phil Garrou in his latest blog posting. To be fair, though, he adds, all the key players in CMOS image sensors have already adopted backside through-silicon vias (TSVs), and the current CIS packages are WLPs, so there is certainly overlap.