Semiconductor International : Wafer Processing Report
October 24, 2008
IN THIS EDITION
NEWS
 
» Despite Losses, Toshiba to Continue Aggressive Investments
» IMEC Has Air Gaps in Post-22 nm Roadmap for Interconnects
» NEXX Licenses Alchimer's Coating Technology
» Environmental Regulations Growing More Complex
» Common Platform Participants Rate High-k as Good Mobile Fit
» Citing High-k Costs, TSMC Plans Dual-Track 28 nm Solutions in 2010
» Ultratech Acquires Patent Rights to IBM Wafer Annealing Technology
» ISMI Recognizes TEL and Applied for Energy Reduction
EDITOR'S PICKS
 
» IBM and the All-In Bet on High-k
» How Might 3-D ICs Come Together?
» Improving Interconnect Reliability via Optimized Barrier/Seed
PRODUCTS
 
» Wafer Edge Pad Conditioners
» Auto-Leveling Inclinometer
» Steam Generator
UPCOMING EVENTS
 
Dear Subscriber,

Despite the somber economic climate, Toshiba is investing heavily to become No. 1 in memory, according to Masakazu Kakumu, vice president of Toshiba’s system LSI division. Meanwhile, there is debate over the cost of high-k/metal gate implementation, which News Editor Dave Lammers explores in his blog, "IBM and the All-In Bet on High-k." Check out these and other highlights below, plus all our wafer processing news and features on our Wafer Processing Technology Channel:

www.semiconductor.net/wafer

Laura Peters, Editor-in-Chief
lpeters@reedbusiness.com

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NEWS

Despite Losses, Toshiba to Continue Aggressive Investments
David Lammers, News Editor -- Semiconductor International, 10/22/2008

In a keynote speech at the ISMI Manufacturing Symposium, Toshiba executive Masakazu Kakumu said the company plans to invest $10B in its chip operations over 2008-2010. He outlined a series of wafer processing throughput improvements to double investment efficiency at the company's wafer fabs. More

IMEC Has Air Gaps in Post-22 nm Roadmap for Interconnects
Laura Peters, Editor-in-Chief -- Semiconductor International, 10/21/2008

Though copper will clearly remain the interconnect material of choice, there may be some material changes in the barriers and capping layers after the 22 nm node, said Rudi Cartuyvels, director of interconnect, packaging and system integration, at IMEC's annual research review meeting. To achieve k<2.0, air gaps must be employed. More

NEXX Licenses Alchimer's Coating Technology
Laura Peters, Editor-in-Chief -- Semiconductor International, 10/8/2008

Alchimer SA (Paris) said it has licensed its eG ViaCoat product for creating conformal copper seed layers for through-silicon via (TSV) applications to NEXX Systems Inc. (Billerica, Mass.), a maker of electroplating tools. The partnership allows the combination of 300 mm tooling with the optimized chemistry and recipes used in the eG ViaCoat for copper seed deposition. More

Environmental Regulations Growing More Complex
David Lammers, News Editor -- Semiconductor International, 10/22/2008

Participants at an ISMI meeting on emerging environment, safety and health (ESH) regulations said the Stockholm Convention on Persistent Organic Pollutants is expected to vote on a ban of PFOS in May. The possible ban is part of an increasingly complex set of environmental regulations, with China taking an ever-dimmer view of potential contaminants. More

Common Platform Participants Rate High-k as Good Mobile Fit
Alexander E. Braun, Senior Editor -- Semiconductor International, 10/2/2008

The Common Platform Technology Forum centered on partnering to defray ever-increasing R&D costs. Speakers said high-k/metal gate technology at the 32 nm node will meet escalating mobile system needs. More

Citing High-k Costs, TSMC Plans Dual-Track 28 nm Solutions in 2010
David Lammers, News Editor -- Semiconductor International, 9/29/2008

TSMC said it will offer both silicon oxynitride (SiON) and high-k/metal gate solutions at the 28 nm node, with early manufacturing starting early in 2010 for the low-power turbo process and in the first half of 2010 for the high-k enabled high-performance process. At this stage, high-k/metal gate process flows can add thousands of dollars in per-wafer processing costs, experts said. More

Ultratech Acquires Patent Rights to IBM Wafer Annealing Technology
Ann Steffora Mutschler, Senior Editor -- Electronic News, 10/9/2008

The agreement covers U.S. and foreign patents for a portfolio including hardware for thermal processing of semiconductor wafers, as well as patents for temperature control and metrology. More

ISMI Recognizes TEL and Applied for Energy Reduction
Business Wire, 10/21/2008

The International Sematech Manufacturing Initiative (ISMI) has recognized Tokyo Electron Ltd. (TEL) and Applied Materials Inc. for their dedication to resource conservation in the semiconductor equipment industry. More

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EDITOR'S PICKS

IBM and the All-In Bet on High-k
David Lammers, News Editor -- Semiconductor International, 10/6/2008

The debate about the worthiness of high-k/metal gate technology brought to mind what Japanese semiconductor managers said about Hajime Sasaki, who ran NEC's semiconductor operation back in the late 1980s: "He knows how to keep the fabs full." More

How Might 3-D ICs Come Together?
Philip Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, N.C. -- Semiconductor International, 10/1/2008

The first production applications for 3-D ICs, CMOS image sensors and stacked memory, are not waiting for a fully developed infrastructure. In Part 1, we review the strong drivers behind 3-D integration and the status of the supporting infrastructure, and Part 2 will explore the commercialization of 3-D IC technology. More

Improving Interconnect Reliability via Optimized Barrier/Seed
H.J. Wu, R. Shaviv, M. Sriram, W. Wu, A. Pradhan, K.J. Park, J. O'loughlin, K. Chattopadhyay, T. Mountsier and G. Dixit, Novellus Systems Inc., San Jose -- Semiconductor International, 10/1/2008

The improvement in the SiCN/Cu interface, along with slower copper drift and reduced copper void growth rate, greatly enhances electromigration performance of copper interconnects with Cu-Al seed. More

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Evolving CMP for Scaling Webcast
In this on-demand webcast, panelists discuss the demands for low-damage processes and excellent uniformity as well as new ways to address those challenges, particularly in copper metallization and barrier steps for interconnects. Panelists include: Mark Buehler of Intel Corp., Jan Vaes of IMEC, Reinhold Dauskardt of Stanford University, and Rajiv Singh of the University of Florida.
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Sponsored by: Levitronix and Jordan Valley

PRODUCTS

Wafer Edge Pad Conditioners

The Diamonex Phoenix Edge is a pad conditioner for CMP of wafers. It produces CMP pad surfaces with significantly smaller asperities and more consistent pad texture.
Morgan Technical Ceramics, Worcestershire, UK
More

Auto-Leveling Inclinometer

The WaferSense Auto Leveling System 2 (ALS2) Vertical is a MEMS sensor that improves vertical accuracy by 10x.
Cyber-Optics Semiconductors Inc., Beaverton, Ore.
More

Steam Generator

The Steamer 501 is a compact, economical system that delivers a steam flow rate of >50 slm. This encourages an increased oxide layer growth rate and uniformity on wafers used for solar cells and wet thermal oxidation.
RASIRC, San Diego
More

UPCOMING EVENTS

Oct. 27-30, 2008: VLSI/ULSI Multilevel Interconnection Conference

Nov. 13-14, 2008: IMEC 3-D Integration Workshop - Taiwan

Copyright 2008 Reed Business Information, a division of Reed Elsevier Inc. All Rights Reserved.
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