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Semiconductor International NewsBreak
TOP STORY... October 14, 2008

IMEC Views 3-D Stacking as System Design
IMEC managers said the research center has made significant progress creating test 3-D ICs, using die-to-die stacking. IMEC's Eric Beyne said achieving coplanar and particle-free surfaces still presents processing challenges. He described the dual-damascene via processing as comparable to traditional front-end interconnect via processing, but with larger features.
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Perspectives From the Leading Edge: Opening the Kimono, Ziptronix Gives Details on DBI Process
Phil Garrou provides more details of the Direct Bond Interconnect (DBI) technology developed at Ziptronix Inc. "Ziptronix has now revealed that in one preferred embodiment the DBI metal is Ni, which can be CMP polished at the same time as the oxide surface without getting any 'cupping' that can happen with some metals like Cu," Garrou writes. "This is obviously a key to the DBI process, i.e. achieving the necessary extremely flat surface so that metal-metal contact occurs when the die (or wafers) are aligned and bonded."

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