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September 3, 2008 |
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IN THIS EDITION |
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NEWS |
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EDITOR'S PICKS |
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PRODUCTS |
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UPCOMING EVENTS |
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Dear Subscriber,
To address the ramifications of the proposed elimination of brominated flame retardants, chlorinated flame retardants and PVC from the electronics supply chain, iNEMI and Intel are hosting a symposium on environmentally friendly materials in Shanghai, China, on Nov. 11-12. The symposium will focus on OEMs' environmental positions and roadmaps, supply chain readiness, challenges such as materials availability, cost and reliability, as well as aim for industry alignment on common solutions to implement this shift in materials. Robin Martin, co-general manager, Intel Assembly and Test, and managing director, Intel Products (Shanghai), will present a keynote address. You can learn more about this issue and the symposium on iNEMI's website: www.inemi.org.
And remember to look for more advanced packaging news and events on our Packaging Technology Channel:
www.semiconductor.net/packaging
Sally Cole Johnson, Contributing Editor
scolejohnson@mac.com |
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Ericsson and STMicroelectronics to Create World Leader in Mobile Platforms
PR Newswire, 8/20/2008
STMicroelectronics and Ericsson announced an agreement to merge Ericsson Mobile Platforms and ST-NXP Wireless into a joint venture. The 50/50 joint venture will have the industry's strongest product offering in semiconductors and platforms for mobile applications and will be an important supplier to Nokia, Samsung, Sony Ericsson, LG and Sharp.More |
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Cadence Withdraws Proposal to Acquire Mentor Graphics
Business Wire, 8/15/2008
Cadence Design Systems Inc. announced that it has withdrawn its proposal to acquire all of the outstanding shares of Mentor Graphics Corp. More |
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Ultratech Management Sees Bright Outlook
Investor's Business Daily, 8/14/2008
Sales growth at Ultratech, a small chip equipment maker, is running ahead of a lot of its larger peers after it lost money from 2005 to 2007. More |
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Tessera Receives Patent Office Action in '627 Patent
Business Wire, 8/13/2008
Tessera Technologies Inc. announced that the U.S. Patent and Trademark Office (PTO) on Aug. 10 issued a second office action in the ongoing ex parte reexamination of Tessera's U.S. Patent No. 6,133,627 (the '627 patent). The patent relates to semiconductor packaging technologies used in a variety of applications. More |
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Sematech to Host 3-D Manufacturing Workshop
Business Wire, 8/18/2008
SEMATECH will host global experts representing a broad spectrum of the semiconductor industry at a workshop designed to explore manufacturing and reliability challenges for three-dimensional integrated circuit (3-D IC) products. The forum, "Manufacturing and Reliability Challenges for 3D ICs using TSVs," will be held in conjunction with the Advanced Metallization Conference, Sept. 25 and 26, at the Del Mar Fairgrounds in San Diego, Calif. More |
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SUSS MicroTec Announces CB Wafer Bonders Series for MEMS
Business Wire, 8/26/2008
SUSS MicroTec announced semi and fully automated wafer bonders for Advanced MEMS devices for the automotive and consumer markets. More |
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Competitive Technologies Announces Sale of Flip-Chip Technology
Globe Newswire, 8/28/2008
Competitive Technologies Inc. announced the sale of the Flip Chip technology patent portfolio, owned by CTT and other investors, to an Asian-based company. The portfolio consists of a group of U.S. and international patents covering the wafer interconnect process, commonly known as flip-chip, because of the manner in which they are mounted to the device for greater efficiency. More |
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Cadence Delivers System-in-Package Miniaturization
Market Wire, 8/18/2008
Cadence Design Systems Inc. announced its SPB 16.2 release, which focuses aggressively on addressing current and emerging chip package design challenges. This latest release delivers advanced IC package/system-in-package (SiP) miniaturization. More |
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'Superatoms' Open Window to Nanoparticle Chemistry
Alexander E. Braun, Senior Editor — Semiconductor International, 8/7/2008
The principles behind the stability and electronic properties of metallic gold nanoclusters have been described, opening the door to new applications for materials, superconductivity and even self-assembly. More |
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STATS ChipPAC to Manufacture Infineon's First-Gen eWLB Products
Sally Cole Johnson, Contributing Editor — 8/28/2008
STATS ChipPAC has signed on to provide manufacturing services for products using Infineon's first-generation embedded wafer-level ball grid array (eWLB) technology at its facility in Yishun, Singapore. eWLB is a fan-out wafer-level packaging technology that uses a combination of traditional front-end and back-end manufacturing techniques with parallel processing of all the chips on the wafer to provide a higher integration level. More |
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TSV Bonding Solution
WaferBOND HT-10.10 is a second-generation spin-on polymer temporary wafer bonding solution. It bonds a device wafer to a temporary carrier to allow thinning and subsequent processing to create TSVs. The bonded wafer pairs have the rigidity necessary for handling during processing.
Brewer Science Inc., Rolla, Mo.
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Electrochemical Process
AquVia was designed to produce conformal, uniform insulation and barrier layers inside a TSV with aspect ratios beyond 10:1. Combined with the company's eG ViaCoat technology, it allows the same tool to be used for deposition of insulation, barrier and seed layers.
Alchimer SA, Santa Barbara, Calif.
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Sept. 7-10, 2008: 2008 KGD Packaging & Test Workshop
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Sept. 15-17, 2008: Advanced Thermal Management and Packaging Materials
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Oct. 13-16, 2008: International Wafer-Level Packaging Conference
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Oct. 13-16, 2008: Advanced Technology Workshop on Thermal Management
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Nov. 2-6, 2008: IMAPS 2008
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