Most Viewed Articles for the Week of August 25, 2008

Our top news story involves a billion dollar investment by the Russian government in a Moscow fab, which will license technology from among IBM, Intel and STMicro to build digital TVs and global positioning systems. Alex Braun reported live from a SEMI forum about the slow immediate growth expected in the semi market, while CIGS PV growth moves along steadily with a new cross-licensing agreement, Mitsubishi's announcement of a 600 MW plant in Nagano Prefecture and a new tool from Veeco. More

Double Patterning Battles Cost, Complexity
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 7/17/2008

Double patterning is not without its challenges, but it nonetheless is positioned as the most promising technology for 32 nm patterning, said participants at the Sokudo Lithography Breakfast Forum held during SEMICON West. More

Self-Aligned Double Patterning Coming
David Lammers, News Editor — Semiconductor International, 7/17/2008

Applied Materials Inc. said that its self-aligned double patterning (SADP) technology is gaining acceptance at key NAND flash manufacturers. More

Etcher Tuned for Double Patterning, Advanced Gates
Laura Peters, Editor-in-Chief — Semiconductor International, 7/13/2008

Lam Research Corp. introduced the Versys Kiyo3x Conductor etch platform to address uniformity considerations of advanced gate and double patterning for 3X logic and flash chipmakers and 4X-5X DRAM makers. More

ASML's Latest Immersion Tool Enables 38 nm Memory
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 7/15/2008

ASML's latest immersion lithography tool, the Twinscan XT:1950i, improves the single-machine overlay to 4 nm, a key parameter in achieving effective double patterning. More

IMEC Reduces Cost of Double Patterning Lithography
Staff — Semiconductor International, 7/14/2008

IMEC and JSR Corp. said they have realized a simplified process using only one etch step to reduce the cost of double patterning. The technique effectively freezes the resist after the first exposure. More

Competing Lithography Technologies Share Heartaches
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 5/21/2008

At the Sematech Litho Forum, IBM's David Medeiros said attention must be paid to the overlay budget in double patterning, including the mask image placement. Another key focus: data prep volumes and the handling of that data for mask creation. More

Webcast: Litho Forum Survey: EUV by 2016?
Moderated by Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 6/3/2008

Bernie Roman, Litho Forum program chair, presents the full results from surveys conducted before and after this year's Sematech Litho Forum. View

Etch's Role in Novel Logic Device Patterning
Thorsten Lill, Applied Materials, and Steffen Schulze, Mentor Graphics — Semiconductor International, 4/1/2008

For 32 and 22 nm devices, splitting the tight pattern pitches of a line array into two separate masks with twice the regular space is one promising solution. However, all double patterning techniques require new EDA tools for layout decomposition, and new design constraints may have to be enforced to ensure layout compliance. More

The Fine Print: Making All Lithography Look Impossible
Aaron Hand, Executive Editor, Semiconductor International, August 13, 2008

During the Device Scaling TechXPOT at SEMICON West, panelists discussed six potential lithography routes: immersion lithography (including high-index and double patterning), EUV lithography, imprint lithography, increased layout regularity, and evolving design flows. Moderator Lars Liebmann offered them up — then tore them down, one by one. Blog

Improving the Way We Change Materials
Laura Peters, Editor-in-Chief — Semiconductor International, 7/17/2008

During a panel discussion organized by Praxair Electronics at SEMICON West 2008, Gurtej Sandhu, director of advanced technology R&D at Micron Technology, said new resist freezing approaches to double patterning look very promising as a method to lower cost. Only one etch is needed. More

Applied Materials Looks at Life Beyond EUV
Alexander E. Braun, Senior Editor — Semiconductor International, 6/3/2008

At a forum organized by Applied Materials Inc., Klaus Schuegraf, vice president of SanDisk, said double patterning solutions should extend current lithography until EUV comes along. However, it is uncertain whether double patterning will be a fully adequate solution beyond the 20 nm generation. More

Double Patterning Drives Computational Upgrades
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/25/2008

Brion Technologies (Santa Clara, Calif.) introduced both a platform upgrade and a new product that are geared toward enabling double patterning lithography techniques at 32 nm and beyond. Tachyon DPT is intended to help chipmakers with pattern splitting and stitching. More