If you have yet to discover why 3-D TSVs are one of the hottest topics in the industry, you can find out by reading Jan Vardaman's article "Why 3-D TSV is Hotter Than Hot." Interested in a flip-chip technology evolution? Be sure to check out "Amkor Unveils High-Performance Flip-Chip Packaging Technology." Want to find out more information about a wire bond tester that may make it possible to non-destructively test wire bond quality in real-time during automated wire bonding? See Laura Peters' "Wire Bond Tester Targets Zero Field Failures." You can find all of these articles here under the "Editor's Picks." Also, remember you can find more advanced packaging news and events on our Semiconductor Packaging Technology Channel:

Sally Cole Johnson, Contributing Editor
scolejohnson@mac.com

New Packaging Technologies Dominate Best of West Awards
Thomas Morrow, Vice President of Global Expositions and Marketing, SEMI, San Jose — Semiconductor International, 7/11/2008

Underscoring the degree of innovation occurring in semiconductor packaging, four of the eight finalists in the Best of West awards were new packaging technologies — three of these serve in 3-D IC applications. More

SUSS MicroTec Unveils 300 mm Mask Aligner for 3-D Packaging
Business Wire, 7/15/2008

At SEMICON West 2008, SUSS MicroTec unveiled the second generation of its MA300 production mask aligner, featuring a dedicated alignment kit for creating 3-D interconnects for applications like chip stacking and 3-D image sensor packaging. More

EV Group Supplies TSV Equipment to STMicroelectronics
PR Newswire, 7/8/2008

EV Group has received a major multi-million-euro order from STMicroelectronics for its 300 mm bonding, alignment and photoresist processing tools. EVG's fully automated tools were successfully installed at STMicro's 300 mm through-silicon via (TSV) pilot line in Crolles, France, and are used in the manufacture of CMOS imaging sensors. More

Gartner Cuts Semi Equipment Forecast to -22.4%
Ann Steffora Mutschler, Senior Editor — Electronic News, 7/10/2008

Heading grimly into the semiconductor manufacturing equipment industry's biggest tradeshow and conference, SEMICON West, market research company Gartner Inc. has cut its semiconductor capital spending forecast by an additional 2.6%, projecting a 22.4% decline for 2008, with little upside potential currently visible for the near-term given that all segments of the semiconductor manufacturing equipment market are reporting decreased spending plans, coupled with an anticipated bursting of the capital spending bubble in memory markets, as well as continued uncertainty in the global economic picture. More

Aehr Test Systems Receives Order for Burn-In and Test System
PR Newswire, 7/14/2008

Antares and Aehr Test Systems announced that they have agreed to work together to address the establishment of a strategic partnership to jointly pursue the high-power, individual temperature control (ITC), test during burn-in (TDBI) market for packaged devices that dissipate up to 75W per device. More

iNEMI Issues Recommendations for Managing Lead-Free Solder Alloys
Sally Cole Johnson, Contributing Editor — Semiconductor International, 7/10/2008

iNEMI has outlined a set of key approaches to help the electronics industry respond to the many issues and challenges emerging in the manufacturing process as a result of numerous lead-free solder alloy options. More

Nvidia Reports Thermal Issues Caused Packaging Failures
Staff — Semiconductor International, 7/3/2008

Nvidia Corp. said some of its notebook-use graphics chips have failed because of packaging materials that could not withstand the "extreme thermal environments" seen in notebook computers. The company will take a one-time charge of $150M-$200M during its second quarter. More

High-Density Packaging Possibilities
Karl Stuber, Senior Director, Test, Assembly and Packaging, SEMI, San Jose — Semiconductor International, 7/15/2008

A recent analysis of a high-end cell phone found 65 active single and multi-chip packages (MCPs) with I/Os ranging from 2 to 447 pins, with the large majority having <200 I/Os. Mobile device manufacturers today are incorporating more than 30 wafer-level chip-scale packages (WLCSPs) into their high-end cell phones. More