Design for Manufacturability — Break on Through
Teresa McLean, Global Exhibitions Marketing Manager, SEMI, San Jose — Semiconductor International, 6/27/2008

With a variety of available tools, users, utilities and implementations, there is no one DFM product, solution or process involving the entire manufacturing system. The Design for Manufacturability Coalition (DFMC) addresses this problem by taking a holistic approach to addressing the needs of the entire system. More

Industry's First Electrical DFM Solution Selected as Best of West Finalist
Thomas Morrow, Vice President of Global Expositions and Marketing, SEMI, San Jose — Semiconductor International, 6/27/2008

For smaller, lower-power, higher-performing devices at the 32 and 22 nm nodes, manufacturability signoff becomes increasingly necessary. One of SEMI's Best of West finalists, Cadence Design Systems, is being recognized for a product that enables variability analysis and optimization for OPC and lithography signoff. More

ATE Industry Maneuvers Around 'Perfect Storm' of Issues at 90 nm and Below
Sally Cole Johnson, Contributing Editor — Semiconductor International, 6/12/2008

Challenges are combining and churning to create a "perfect storm" for ATE vendors to maneuver around, while they also take on a myriad of design sensitivity issues occurring at 90 nm and below. Wafer fab process improvements and design/design for test (DFT) needs show potential to push system-on-a-chip (SoC) to the forefront. More

Synopsys Unveils Faster Router
Laura Peters, Editor-in-Chief — Semiconductor International, 5/27/2008

Responding to the need to take better advantage of the multicore microprocessor architectures and solve 45 nm design for manufacturability (DFM) challenges in IC design, Synopsys Inc. (Mountain View, Calif.) introduced the Zroute compiler router. More

How to Detect Non-Overlay Misalignment Errors?
Laura Peters, Editor-in-Chief — Semiconductor International, 5/8/2008

Engineers at Semiconductor Manufacturing International Corp. (SMIC, Shanghai) were confronted with an unusual problem in their DRAM fab — how to detect a misalignment error that was not caused by an overlay problem. More

Electromigration-Induced Failures in Plastic Encapsulated IC Packages
William Eslinger, Boston Scientific, St. Paul, Minn. — Semiconductor International, 6/1/2008

A commercial CMOS digital potentiometer IC in an eight-pin small outline transistor package was demonstrating field failures after ~1 month of operation. Systematic failure analysis led to the identification of the failure mechanism: post-manufacture, metal migration inside the plastic-encapsulated package. More

Views on News: RCP and the Front-End/Back-End Convergence
David Lammers, News Editor — Semiconductor International, 5/23/2008

Freescale Semiconductor Inc.'s redistributed chip packaging (RCP) technology is an effort that cries out for standards and partners. Freescale's RCP and the embedded wafer-level ball grid array (eWLB) technology from Infineon Technologies AG are attempting to take advantage of the same opportunities. Blog

ITRS Yield Enhancement: The End Justifies The Means
Laura Peters, Editor-in-Chief — Semiconductor International, 3/12/2008

The 2007 Update of the Yield Enhancement chapter of the International Technology Roadmap for Semiconductors (ITRS) defines the difficult challenges in the short term (≥22 nm) and long term (<22 nm), with the approximate defect budgets needed to obtain acceptable yields on semiconductor devices at those nodes. More

Views on News: TSMC and the Reverse Temperature Effect
David Lammers, News Editor — Semiconductor International, 4/30/2008

TSMC would prefer that its leading-edge customers go directly from 65 to 40 nm design rules, making 40 nm much more than an afterthought 0.9× linear shrink. Blog

Silicon Valley PV Development Center Launches
David Lammers, News Editor — Semiconductor International, 6/25/2008

SVTC Technologies has set up the the Silicon Valley Photovoltaic Development Center in San Jose, with Roth & Rau AG and JA Solar Co. as initial partners. Kurt Laetz, SVTC Solar program manager, said, "The vision is for us to be a place where customers can come and have the entire suite of support services for their development efforts." More

Most Viewed Articles for the Week of June 23, 2008

News from last week's VLSI Technology Symposium continued to be popular this week, with word from IBM about its high-k advantage over TSMC taking top honors. Other articles getting lots of views include the latest MEMS projections, the launch of the Silicon Valley Photovoltaic Development Center, Dow Corning’s e-beam resist, and Lam’s new etch tools that enable double patterning applications. More