Toshiba and SMIC gave us some welcome news in this uncertain economic climate with plans to build multiple fabs. Toshiba will build two fabs in Japan and SMIC will build two fabs in China. Meanwhile, equipment start-ups are alive and well. A company called Surfect Technologies has developed an innovative single-wafer electrochemical deposition technology using ultrasonic energy. Remember that you can always find other useful information at our Wafer Processing Technology Channel:

Peter Singer, Editor-in-Chief
sieditor@aol.com

Toshiba Plans New Memory Fabs
David Lammers, News Editor — Semiconductor International, 2/19/2008

Toshiba Corp. (Tokyo) announced that it will build two fabs in parallel, one at its existing memory complex in Yokkaichi and another in Iwate in northeastern Japan. Separately, SanDisk Corp. (Milpitas, Calif.) and Toshiba said they have signed a non-binding memorandum of understanding to form a new production joint venture and construct a new 300 mm wafer fab in Japan. More

SMIC to Expand With Two Fabs in Shenzhen
David Lammers, News Editor — Semiconductor International, 1/30/2008

Semiconductor Manufacturing International Corp. (SMIC, Shanghai) will launch a semiconductor manufacturing complex in Shenzhen in cooperation with the Shenzhen municipal government. More

Sumitomo Makes Takeover Bid for Axcelis
David Lammers, News Editor — Semiconductor International, 2/11/2008

Sumitomo Heavy Industries Ltd. (SHI, Tokyo) took the wraps off of an unsolicited takeover bid for Axcelis Technologies Inc. (Beverly, Mass). More

Roadmap Dictated by Flash, More Than Moore
Laura Peters, Lead Technical Editor — Semiconductor International, 1/25/2008

The 2007 edition of the International Technology Roadmap for Semiconductors (ITRS) projects the technology targets needed to continue to produce semiconductor devices cost-effectively through the year 2022. A significant new focus is the emphasis on More than Moore, the integration of various types of devices, as is deemed cost-effective, either on the same chip or in the same package. More

TI Pushes Junctions in 45 nm Transistors
David Lammers, News Editor — Semiconductor International, 2/7/2008

Texas Instruments Inc. (TI, Dallas) technology managers said improvements to junction engineering, supported by millisecond annealing techniques, play a key role in TI's 45 nm transistor technology, now winding its way toward mass production in the second half of this year. The biggest challenge was to control leakage while scaling the silicon oxynitride (SiON) gate dielectric by several angstroms and shortening the gate length. More

Heterogeneous Channels: A Goal of EC's 'Duallogic' Project
Staff — Semiconductor International, 2/11/2008

A European project to create dual-channel CMOS was announced, with the goal of combining germanium PMOS and III-V NMOS channels for post-22 nm CMOS. More

Stanford Researchers Demonstrate GHz-Speed CNT Interconnects
David Lammers, News Editor — Semiconductor International, 2/16/2008

Researchers at Stanford University (Palo Alto, Calif.) have developed a method of placing multi-walled carbon nanotubes as wires, with gigahertz-level interconnect performance observed for the first time. More

Green Chips: IC Makers Looking to Cash In
Peter Singer, Editor-in-Chief — Semiconductor International, 2/5/2008

The global explosion in information technology, combined with rapidly escalating energy costs, has chipmakers asking how much does it really cost to run today's computers, and what can be done to provide more energy-efficient solutions? More