Semiconductor International : Lithography Report
January 9, 2008
IN THIS EDITION
NEWS
 
» Nanoimprint Litho Ramps for HDDs, CMOS
» ITRS Lithography Update Weeds Out 45 nm Options
» TSMC Announces Multilayer Mask Service
» ASML, Zeiss Cross-License Lithography Patents With Canon
» Canon Immersion Scanner Uses Twin-Stage Pipeline Scheme
» Sematech: Lack of Litho Reference Measurements a Concern
» GenISys Builds Team for E-Beam Correction
» NIST Paper Reveals Nanoscale Details of Photolithography Process
EDITOR'S PICKS
 
» 32 nm Marked by Litho, Transistor Changes
» 2008 Economic Forecast: Fairly Unpredictable
» Executive Outlook: Driving Productivity, CoO in 2008
PRODUCTS
 
» ArF Excimer Laser
» Bilayer Photoresist
UPCOMING EVENTS
 
Dear Subscriber,

Happy New Year! Flipping the calendar to the new year always has a way of getting me excited about the building news on the lithography front. With SPIE's Advanced Lithography conference less than two months away, the litho news buzz is starting to get a little louder. Although not everybody is coming forward with all the low-down at this point, it sounds like we will see a lot of key results at SPIE. In the meantime, we've been catching up with some key players to find out about the latest progress in immersion, EUV, nanoimprint, and more. Check out the latest news and technical articles below, then check back regularly at our Lithography Info Channel:
www.semiconductor.net/lithography

Aaron Hand, Executive Editor, Electronic Media
ahand@reedbusiness.com

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Hear the latest research at SPIE Advanced Lithography
SPIE Advanced Lithography brings together the top researchers and engineers in the semiconductor lithography industry. See the most recent and critical developments in chip design, fabrication, and manufacturing. Join your colleagues in San Jose for the must-attend event of the year, 24-29 February 2008
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NEWS

Nanoimprint Litho Ramps for HDDs, CMOS
Alexander E. Braun, Senior Editor — Semiconductor International, 1/8/2008

Nanoimprint lithography is moving to commercial acceptance, with the hard disk drive industry using the technique next year and NAND memory manufacturers following soon after, according to Mark Melliar-Smith, CEO for Molecular Imprints. IBM has used nanoimprint to create finFET memories. More
Listen to the interview

ITRS Lithography Update Weeds Out 45 nm Options
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 12/21/2007

With leading chipmakers implementing 45 nm half-pitch production today, a significant change to the latest version of the ITRS has been the weeding out of 45 nm potential solutions that simply aren't ready for that node, according to Mike Lercel, lithography director at Sematech and also U.S. chair of the lithography ITRS working group. More
Listen to the interview
Read the transcript

TSMC Announces Multilayer Mask Service
PR Newswire, 12/27/2007

Taiwan Semiconductor Manufacturing Co. Ltd. announced the foundry industry's first multilayer mask service (MLM) for advanced process technologies. More

ASML, Zeiss Cross-License Lithography Patents With Canon
Ann Steffora Mutschler, Senior Editor — Electronic News, 12/21/2007

Lithography giant ASML Holding NV (Veldhoven, Netherlands) and lithography optics provider Carl Zeiss SMT (Oberkochen, Germany) said today that each company has signed a global cross-licensing agreement with Canon Inc. for patents in their respective fields of semiconductor lithography and optical components. More

Canon Immersion Scanner Uses Twin-Stage Pipeline Scheme
Kenji Tsuda, Asia Contributing Editor — Semiconductor International, 12/17/2007

Canon Inc. (Tokyo) disclosed some details of its long-awaited AS-7 ArF immersion scanner. The company said it has a more efficient technique of simulating the lens distortion, as thermal distortion correction and alignment correction are performed simultaneously. More

Sematech: Lack of Litho Reference Measurements a Concern
Alexander E. Braun, Senior Editor — Semiconductor International, 12/14/2007

With the industry inexorably headed toward the 32 nm node, lithography increasingly faces demands on CD and overlay metrology, and in producing the necessary models required to work at this node. More

GenISys Builds Team for E-Beam Correction
Business Wire, 12/13/2007

GenISys GmbH, a provider of software for optimization of microstructure fabrication processes, today announced it has signed an agreement with the Fraunhofer Institute of Integrated Systems and Device Technology (IISB) for the development and licensing of advanced 3-D resist modeling techniques for e-beam and proximity lithography. More

NIST Paper Reveals Nanoscale Details of Photolithography Process
US Fed News, 12/12/2007

Scientists at the National Institute of Standards and Technology (NIST) have made the first direct measurements of the infinitesimal expansion and collapse of thin polymer films used in the manufacture of advanced semiconductor devices. It's a matter of only a couple of nanometers, but it can be enough to affect the performance of next-generation chip manufacturing. More

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Feb. 19: Preparing for High-Volume Immersion Lithography
Broadcast in both English and Japanese, this webcast will look at the most pressing challenges facing immersion lithography and the solutions that are being worked on. Panelists include: Kurt Ronse, IMEC; Burn Lin, TSMC; and Bryan Rice, Sematech.
Register Now!

Sponsored by: ASML
EDITOR'S PICKS

32 nm Marked by Litho, Transistor Changes
Laura Peters, Lead Technical Editor — Semiconductor International, 1/1/2008

The transition from 45 to 32 nm is likely to involve some key material changes and a major change in lithography to double patterning for critical layers. Selections will be driven by costs and specific product needs. More

2008 Economic Forecast: Fairly Unpredictable
Staff — Semiconductor International, 1/1/2008

With the low average selling price of memory devices and reductions in capex plans, many forecasters are indicating a slower initial 2008, although the duration of a slowdown is hard to quantify. More

Executive Outlook: Driving Productivity, CoO in 2008
Staff — Semiconductor International, 1/1/2008

Shrinking margins are forcing even greater emphasis on efficiency, productivity and cost-of-ownership. Even so, technology challenges have not let up. Thirty-four industry executives describe these challenges, including Franklin Kalk, Toppan Photomasks; Mike Fister, Cadence Design Systems; Walden Rhines, Mentor Graphics; Eric Meurice, ASML; Mark Melliar-Smith, Molecular Imprints; and Tracy Weed, Synopsys. More

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January 22: Highlights of the 2007 ITRS
In this webcast, Alan Allan, Intel External Programs Staff Engineer and member of the IRC, will explain the important changes relative to past years and significant additions to the roadmap. He will then be joined by the chairmen of several of the key technology working groups to answer live questions from the audience.
Register Now!

Sponsored by: TEL and Particle Measuring Systems

PRODUCTS

ArF Excimer Laser

The GT62A was designed for double patterning immersion lithography tools. It has an emission wavelength of 193 nm, an output of 90 W and a repetition rate of 6000 Hz.
Gigaphoton Inc., Oyama, Japan
More

Bilayer Photoresist

This silicon-infused bilayer photoresist uses silicon polymer in the imaging layer to provide advanced etch selectivity. This enables the use of thinner photoresist layers, improving pattern resolution and allowing for smaller patterns to be transferred onto target wafers without pattern collapse issues.
Tokyo Ohka Kogyo Co. Ltd., Tokyo; Dow Corning Corp., Midland, Mich.
More

UPCOMING EVENTS

Jan. 22, 2008: 2007 Edition of the ITRS

Feb. 24-29, 2008: SPIE Advanced Lithography

Copyright 2008 Reed Business Information, a division of Reed Elsevier Inc. All Rights Reserved.
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