December was rife with wafer processing news, including 45 and 32 nm process details that emerged from the International Electron Devices Meeting (IEDM), IBM's licensing of its 45 nm tech to China's Semiconductor Manufacturing International Corp. (SMIC, Shanghai), and a record-breaking
1 THz transistor produced by Northrop Grumman Corp. (Redondo Beach, Calif.). Remember that you can always find other useful information at our Wafer Processing Technology Channel:

Peter Singer, Editor-in-Chief
sieditor@aol.com

Pellerin Peers Down AMD Process Options
David Lammers, News Editor — Semiconductor International, 12/18/2007

John Pellerin, director of logic technology development at Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), is sitting in one of the industry's hot seats now, as the company seeks to get back on track with the design and manufacturing synergies that served it so well in 2006. More

Intel Takes 45 nm High-k/Metal Gate Process to IEDM
David Lammers, News Editor — Semiconductor International, 12/14/2007

Intel Corp. (Santa Clara, Calif.) provided some details of its 45 nm high-k/metal gate process flow at the International Electron Devices Meeting (IEDM) in Washington, D.C., although key elements of the pFET electrode metal remained shrouded. More

IBM Licenses 45 nm Technology to SMIC
Staff — Semiconductor International, 12/26/2007

IBM Corp. (Armonk, N.Y.) recently said that it has licensed its 45 nm bulk CMOS technology to foundry Semiconductor Manufacturing International Corp. (SMIC, Shanghai). More

1 THz InP Transistor Claims Speed Record
Peter Singer, Editor-in-Chief — Semiconductor International, 12/21/2007

Northrop Grumman Corp. (Redondo Beach, Calif.) is claiming a new world record for transistor speed with an indium phosphide-based high-electron-mobility transistor (InP HEMT). The device has a maximum frequency of operation of >1 THz (1000 GHz). More

IMEC Reports Progress on High-k/Metal Gates
Laura Peters, Lead Technical Editor — Semiconductor International, 12/11/2007

At IEEE's International Electron Devices Meeting (IEDM), recently held in Washington, D.C., IMEC (Leuven, Belgium) reported significant progress in improving the performance of planar CMOS using hafnium-based high-k dielectrics and tantalum carbide metal gates targeting the 32 nm node. More

Toshiba Joins IBM Alliance for 32 nm Bulk Process Development
David Lammers, News Editor — Semiconductor International, 12/18/2007

IBM Corp. (Armonk, N.Y.) and Toshiba Corp. (Tokyo) recently announced that they have extended their relationship at the IBM-led process development alliance, entering into a joint development agreement on 32 nm bulk CMOS process technology. The work will be conducted as part of the now seven-company alliance, based in East Fishkill, N.Y. More

IBM Alliance Develops 32 nm High- k/Metal Gate SRAM
David Lammers, News Editor — Semiconductor International, 12/9/2007

IBM Corp. (Armonk, N.Y.) said that it has developed a test SRAM array using 32 nm high-k/metal gate process technology, an achievement that puts IBM and its Fishkill alliance development partners on track to introduce 32 nm technology in the second half of 2009. More