The 2007 International Technology Roadmap for Semiconductors (ITRS) International Technology Working Group (ITWG) chapters are now online at the 2007 ITRS Reports page. Clean processing challenges are included throughout many chapters, but two to focus on are Front End Processes and Yield Management. Remember that you can always find other useful information at our Clean Processing Technology Channel:
www.semiconductor.net/clean

Peter Singer, Editor-in-Chief
sieditor@aol.com

ITRS Yield Enhancement: The End Justifies The Means
Laura Peters, Lead Technical Editor — Semiconductor International, 3/12/2008

The 2007 Update of the Yield Enhancement chapter of the International Technology Roadmap for Semiconductors (ITRS) was recently released, and it defines the difficult challenges in the short term (≥22 nm) and long term (<22 nm), with the approximate defect budgets needed to obtain acceptable yields on semiconductor devices at those nodes. More

TSMC Develops Resist Ashing Method
US Fed News, 2/28/2008

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) inventors were awarded a patent for a "method for forming a damascene structure by providing a single process solution for resist ashing while avoiding and repairing plasma etching damage as well as removing absorbed moisture in the dielectric layer." More

AMAT Develops Wafer Cleaning Method
US Fed News, 3/10/2008

A patent was awarded to Applied Materials for "an apparatus for wet processing individual wafers comprising; a means for holding the wafer; a means for providing acoustic energy to a non-device side of the wafer; and a means for flowing a fluid onto a device side of the wafer." More

Nokia Slips in Greenpeace Green Electronics Ranking
Suzanne Deffree, Managing Editor, News — Electronic News, 3/18/2008

Nokia is the latest company to slip in Greenpeace's rankings. The environmental organization recently released its latest edition of the "Greenpeace Guide to Greener Electronics," reporting that Nokia has fallen to third place as a result of "poor take-back practices" in India and Russia. More

SRC: Nanostructures Require Monitoring at Molecular, Atomic Levels
Alexander E. Braun, Senior Editor — Semiconductor International, 3/13/2008

The development of nanotechnology to its full capabilities requires the ability to cope with things like quantum effects; attaining this will require unprecedented advances in metrology. More

Lam Research Completes Offer for SEZ
Business Wire, 3/11/2008

Lam Research Corp. announced the close of the offer for the SEZ Group. Approximately 95% of the outstanding shares were tendered in the offer. More

Extending Lifetime of Critical Seals in HDP-CVD Processes
Michele Vigliotti, Semiconductor Consultant Europe, DuPont Performance Elastomers, Geneva, Switzerland — Semiconductor International, 3/1/2008

Recent test results on 200 and 300 mm CVD platforms show that a next-generation perfluoroelastomer seal material offers improvements in seal life, downtime and replacement costs. More

Fab-Wide SPR Speeds Yield Improvement
Andrew Drozda-Freeman, Mike McIntyre, Mike Retersdorf and Chris Wooten, Advanced Micro Devices, Sunnyvale, Calif.; Prasad Bachiraju, Xin Song and Len LaBua, Rudolph Technologies Inc., Flanders, N.J. — Semiconductor International, 3/1/2008

Spatial pattern recognition (SPR) technology can speed the correction of yield-robbing problems. The challenge is to deploy a system capable of processing the enormous amount of data generated in modern fabs, and then organize it for fast and consistent problem solving. More

Controlling Plating Baths in TSV Applications
Michael Pavlov, Eugene Shalyt and Peter Bratin, ECI Technology, Totowa, N.J. — Semiconductor International, 3/1/2008

When combined with non-reagent techniques, CVS analysis can ensure appropriate concentrations of inorganic components in electroplating baths, a necessary step in bringing through-silicon via (TSV) processes to production-worthy status. More