Through-Silicon Vias: Ready for Volume Manufacturing?
Peter Singer, Editor-in-Chief — Semiconductor International, 3/1/2008

IDMs, foundries and packaging houses are now developing capabilities for through-silicon vias, but more work needs to be done to address manufacturing costs. More

Technology Platform Integrates High-Performance SiP Modules
G. Carchon and G. Posada, IMEC, Leuven, Belgium — Semiconductor International, 3/1/2008

Using a high-resistivity silicon interposer, thin-film technologies and through-substrate vias, 3-D integration of high-quality passives and high-speed digital devices becomes possible. More

Web Exclusive: Controlling Plating Baths in TSV Applications
Michael Pavlov, Eugene Shalyt and Peter Bratin, ECI Technology, Totowa, N.J. — Semiconductor International, 3/1/2008

When combined with non-reagent techniques, CVS analysis can ensure appropriate concentrations of inorganic components in electroplating baths, a necessary step in bringing through-silicon via (TSV) processes to production-worthy status. More

What's Delaying the Adoption of 3-D TSV?
Jan Vardaman, President, TechSearch International Inc., Austin, Texas — Semiconductor International, 3/1/2008

Through-silicon via (TSV) is the latest in a progression of technologies for stacking silicon devices in 3-D. Placing and wiring devices in 3-D promises higher clock rates, lower power dissipation, and higher integration density. 3-D TSV technology will be adopted in many applications because it solves issues related to electrical performance, memory latency, power, and noise on and off the chip. More

3-D Gets Past 'Chicken or Egg' Problem
Laura Peters, Lead Technical Editor — Semiconductor International, 3/1/2008

When IMEC (Leuven, Belgium) announced its expanded programs in 3-D at its annual meeting last year, Eric Beyne, scientific director of packaging, interconnect and systems integration, admitted that "3-D design suffers from a 'chicken or egg' problem." Users that are evaluating the cost trade-offs of 3-D integration need design tools to evaluate the benefits of manufacturing in 3-D (Z direction) vs. 2-D. However, the EDA community will not supply such tools until there exists a specific and large market for 3-D design tools. More

STMicro Announces More TSV CMOS Image Sensor Packaging Capacity
Phil Garrou, Contributing Editor — Semiconductor International 3/05/2008

STMicro claims that its latest 2M pixel mobile-phone camera module, VD6725, is the world's smallest single-chip camera sensor for mobile applications. The VD6725 is available in STMicro's through-silicon via (TSV) wafer-level package, which enables the production of reflowable camera modules. These are soldered directly on the phone motherboard, which saves cost, space and time compared with the process of fixing traditional camera modules in the board socket. Blog

A Rose By Any Other Name is Not 3-D IC Integration
Phil Garrou, Contributing Editor — Semiconductor International, 11/20/2007

People are beginning to define 3-D as whatever it is that they happen to be doing. This Clintonian effort to spin 3-D into their desired activity, will, in the end, only cause confusion in our community. For instance, in the August/September issue of Chip Scale Review, Belgacem Haba of Tessera presented a very nice review of the evolution of "3-D stacking." By my way of thinking, 3-D stacking, whether using wire bonding or edge connections (irvine sensors or vertical circuits), is 3-D packaging, to be sure, but not 3-D IC integration. The easiest way to spot 3-D IC integration is to look for three things: thinning, bonding and through-silicon (or other semiconductor) vias. Blog

New WLP Technologies Abound
Yole Développement Staff — Semiconductor International, 11/30/2007

Semiconductor chips face constant pressure for increased performances while still decreasing their size. At the same time, their packages must be able to accommodate new functionalities. The ever-expanding consumer electronics market is a particularly strong driver of packaging innovations, such as wafer-level packaging (WLP) and 3-D ICs. More

Heat, Stacking, Interconnect at Forefront of Packaging Development
Alexander E. Braun, Senior Editor — Semiconductor International, 11/14/2007

Thermal considerations, stacking and connecting electronics to the outside world continue to be major packaging concerns. Although significant technical hurdles arising from the endemic shrinking of architectures and system-in-a-chip (SiC) configurations continually raise the bar, research progresses to balance the technology equation. At the 40th International IMAPS symposium, successful results of advanced work in the packaging field were reported by those investigating options. More

TSV 3-D Packaging on Track for 2008
Markus Wimplinger, EV Group, St. Florian, Austria — Semiconductor International, 11/1/2007

According to the 2006 International Technology Roadmap for Semiconductors (ITRS), interconnect schemes represent one of the key next-generation manufacturing challenges due to variability associated with, among other things, trench and via depth and profile, as well as thinning caused by cleaning and chemical mechanical planarization (CMP). More