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March 5, 2008 |
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IN THIS EDITION |
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NEWS |
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EDITOR'S PICKS |
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PRODUCTS |
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UPCOMING EVENTS |
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Dear Subscriber,
3-D through-silicon vias (TSVs). They've been a hot industry topic for more than a year now, but are they ready for volume manufacturing? What factors are contributing to the delay in their adoption? For some perspective and answers, check out the Editor's Picks section below to see what Pete Singer, Laura Peters and Jan Vardaman are saying. And you're invited to tune in to SI's "Through-Silicon Vias: Ready for Prime Time?" webcast on March 25th for further discussion on the topic. Remember you can always find more packaging news and events on our Packaging Technology Channel:
www.semiconductor.net/packaging
Sally Cole Johnson, Contributing Editor
scolejohnson@mac.com |
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ASE Inc. Seeks to Buy ASE Test Ltd.
PR Newswire Asia, 3/4/2008
Advanced Semiconductor Engineering Inc. (ASE) has entered into a syndicated loan agreement with a banking syndicate led by Citibank NA, Taipei Branch, for a NT$24.75 billion term loan facility. Subject to the terms and conditions of the syndicated loan agreement, the facility may be drawn by ASE Inc. on or prior to June 3, 2008, to finance a portion of the consideration for the proposed acquisition by ASE Inc. of the outstanding ordinary shares of ASE Test Ltd., a majority-owned subsidiary of ASE Inc., held by ASE Test shareholders other than ASE Inc. and its subsidiaries by way of a scheme of arrangement under Singapore law. More |
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ASAT Holdings Pre-Announces Higher-Than-Expected 3Q Revenues
PR Newswire, 3/4/2008
ASAT Holdings Ltd., a global provider of semiconductor package design, assembly and test services, expects revenue for the third quarter of fiscal 2008, ended Jan. 31, 2008, will be ~$41.7M, representing an increase of ~4% above second quarter fiscal 2008 revenue of $40.2M. It is also above the guidance the company provided on Jan. 14, 2008, of revenue being inline with the prior quarter. More |
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Siliconware Wins Against Tessera in Patent Reexamination
Business Wire, 3/4/2008
On Feb. 29, 2008, the Patent Office issued an Official Action rejecting Tessera's 6,133,627 patent in ex parte reexamination. The Patent Office rejected every claim of the '627 patent that is in reexamination. More |
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Aptina Imaging Announces Camera Phone Packaging Technique
Business Wire, 3/4/2008
It doesn't stop with a new name. Aptina Imaging, a division of Micron Technology Inc., unveiled some new imaging technology initiatives enabling high-quality picture-taking experiences across the entire spectrum of applications, from the most cost-sensitive mobile phones to high-performance point-and-shoot digital cameras. More |
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Accretech Joins Sematech's 3-D Interconnect Program
Business Wire, 2/27/2008
Accretech Tokyo Seimitsu, a manufacturer of precision measuring and semiconductor manufacturing equipment, and Sematech, the global consortium of chipmakers, announced that Accretech has become an associate member in Sematech's 3-D Interconnect Program located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. More |
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Zygo Acquires Assets of Solvision
Market Wire, 2/28/2008
Zygo Corp. has acquired the assets of Solvision Inc., a Canadian-based company, including the shares of its Singapore subsidiary. With this acquisition, Zygo enters the market for inline inspection of flip-chip substrates and packaged ICs. Included in the acquisition is the patented Fast Moire Interferometer (FMI) technology for rapid 3-D inspection. More |
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Through-Silicon Vias: Ready for Volume Manufacturing?
Peter Singer, Editor-in-Chief — Semiconductor International, 3/1/2008
Much has been written about the many drivers behind 3-D integration, a technology where chips are thinned, stacked and interconnected, which greatly increases density as well as performance. Chip-to-chip connections have, to date, been accomplished with wire bonding, sometimes to eight or more stacked die, but this is limited in terms of the number of connections (I/Os) and electrical performance. In the near future, perhaps within the next two years, the industry is likely to shift to an approach where the connections are made directly through the silicon. More |
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What's Delaying the Adoption of 3-D TSV?
Jan Vardaman, President, TechSearch International Inc., Austin, Texas — Semiconductor International, 3/1/2008
Through-silicon via (TSV) is the latest in a progression of technologies for stacking silicon devices in 3-D. Placing and wiring devices in 3-D promises higher clock rates, lower power dissipation, and higher integration density. 3-D TSV technology will be adopted in many applications because it solves issues related to electrical performance, memory latency, power, and noise on and off the chip. For some applications, a high-bandwidth memory interface to the logic has been the main driver for the development of TSV technology. More |
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3-D Gets Past 'Chicken or Egg' Problem
Laura Peters, Lead Technical Editor — Semiconductor International, 3/1/2008
When IMEC (Leuven, Belgium) announced its expanded programs in 3-D at its annual meeting last year, Eric Beyne, scientific director of packaging, interconnect and systems integration, admitted that "3-D design suffers from a 'chicken or egg' problem." Users that are evaluating the cost trade-offs of 3-D integration need design tools to evaluate the benefits of manufacturing in 3-D (Z direction) vs. 2-D. However, the EDA community will not supply such tools until there exists a specific and large market for 3-D design tools. More |
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QFN Socket
Quatrix Kelvin QFN is a test socket that uses a single set of photolithographic-based contacts with two distinct electrical connections per terminal on an IC package.
Antares Advanced Test Technologies, Vancouver, Wash.
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Mini Imager
The Quadrus MINI Velocity is an autofocus imager that consistently reads linear and 2-D codes moving as fast as 100 in/sec for packaging.
Microscan Systems, Renton, Wash.
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Thermal Interface Sleeves
A stock series of 14 sleeve-shaped thermal interface extrusions were developed for semiconductor packages and thermistors. The highly efficient sleeves are available in three Sarcon formulations and will fit TO-220, TO-3PF and TO-3PL type transistors and similarly shaped electronic components.
Fujipoly America, Carteret, N.J.
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March 11-12, 2008: 3-D All Silicon System Module
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March 13, 2008: Workshop on Wafer-Level MEMS Testing
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March 17-20, 2008: International Device Packaging Conference and Exhibition
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March 25, 2008: Webcast: Through-Silicon Vias: Ready for Prime Time?
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