LuAG, Other High-Index Immersion Elements Get Needed Boost
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/29/2008

Although most chipmakers will use immersion lithography at the 45 nm node, it's unclear what the best option will be at 32 nm. One option being considered as a possible extension of water-based immersion is immersion lithography using high-index materials. Until this week, however, the prospects for really making a go of it were dim. More

Applied Materials: Patterning Requires Innovative Metrology
Alexander E. Braun, Senior Editor — Semiconductor International, 2/28/2008

Applied Materials concurrently held its 12th Annual Technology Forum with this week's SPIE Advanced Lithography Conference in San Jose. Among several subjects, panelists considered what is needed from metrology providers. The opinion was that it would be desirable to have the means to rapidly translate the knowledge that originates during development into hardware and software tools that can be used at every level in the fab. More

Lithography Answers Blowin' in our Wind?
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/28/2008

As is often the case during the nighttime panels at SPIE, there was a fair bit of silliness in Tuesday panel discussion, "Future Projection Lithography: Optical or EUV?" It's a serious enough question, but after a very long day of listening to detailed technical presentations, attending customer/supplier meetings, and perusing the exhibit floor, these leaders of the teams trying to find answers to extremely difficult lithographic challenges were ready to loosen up a bit. The tone was set very aptly by IBM's Kit Ausschnitt, who entertained the audience with a reading of his latest musical adaptation of Bob Dylan's "Blowin' in the Wind." Blog

SPIE: Metrology Must Provide More Accuracy
Alexander E. Braun, Senior Editor — Semiconductor International, 2/27/2008

At the SPIE Advanced Lithography Conference being held this week in San Jose, several of the papers presented so far in the metrology area indicate a significant shift in the importance of accuracy vs. precision. While precision's importance is obvious, the focus on accuracy is definitely becoming sharper — not just for repeatable measurements, but for calibration to standards and National Institute of Standards and Technology (NIST) traceability. More

Sematech Buys MII Imprint Stepper for 32 nm Development
PR Newswire, 2/26/2008

Austin-based Molecular Imprints Inc. (MII) announced that Sematech has purchased MII's latest-generation semiconductor imprint lithography system — the Imprio 300. The nanoimprint tool will be delivered to Sematech at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany in mid-2008 to support 32 nm development activities. More
Learn more about the Imprio 300

Mapper Receives Subsidy From EU's 'Magic' Program
Staff — Semiconductor International, 2/27/2008

Mapper Lithography (Delft, Netherlands) said it has received a 3.5 million euro (US$5.3M) subsidy from a new 12 million euro (US$18.1M) European Union (EU) program called maskless lithography for IC manufacturing (MAGIC). Mapper, founded in 2001, is developing a direct write system that uses parallel electron beams to write patterns without a mask. According to the company, the machine uses light to direct the electron beams individually and incorporates a MEMS lens arrays to accurately focus the parallel electron beams. More

Sematech, Zeiss Report Progress on Mask Metrology Tool
Staff — Semiconductor International, 2/25/2008

A team of more than 40 engineers at Carl Zeiss SMT (Jena, Germany), working with the lithography program of Sematech (Albany, N.Y.), announced design completion of the next-generation Photomask Registration and Overlay Metrology system (PROVE) for mask pattern alignment and registration. The tool is targeted for production by the end of next year, with mask manufacturers as the primary customers. More

IBM, AMD Demo First 'Full-Field' EUV Test Chip
Ann Steffora Mutschler, Senior Editor — Electronic News, 2/26/2008

At the SPIE Advanced Lithography conference being held this week in San Jose, research partners Advanced Micro Devices (AMD) and IBM announced a working test chip that uses extreme ultraviolet (EUV) lithography for the critical first layer of metal connections across the entire chip, compared with previous projects that used EUV for working chip components that were only "narrow field" and covered just a small portion of the design. More

Double Patterning Drives Computational Upgrades
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/25/2008

Brion Technologies introduced both a platform upgrade and a new product that are geared toward enabling double patterning lithography techniques at 32 nm and beyond. Tachyon DPT has been released specifically to help chipmakers with pattern splitting and stitching. Tachyon 2.5, meanwhile, is an upgrade to the company's flagship Tachyon computational lithography platform, providing the speed-up necessary for the increased computational load that double patterning will bring with it. "We see an explosion coming in the computational needs from the extension of 193 down to 22 nm," said Neal Callan, vice president of product operations at Brion. More

Toppan Photomasks, Anchor Announce DFM Tool
Business Wire, 2/27/2008

Toppan Photomasks Inc. introduced a new DFM tool that will shorten cycle time and reduce risk in chip design through an exception dispositioning process for identifying and analyzing defects and design errors. More

Tela Innovations Unveils Strategy, Technology
Business Wire, 2/27/2008

Tela Innovations, an early-stage technology company focused on addressing the challenges of scaling semiconductor manufacturing to 45 nm and beyond, unveiled its business strategy and technology vision for using on-grid, straight-line, 1-D layout structures to provide a more efficient and reliable way to design and manufacture next-generation chips. Details of the solution were disclosed at the SPIE Advanced Lithography Conference in joint presentations from Tela, ASML/Brion and Applied Materials. More

Rohm and Haas, IBM Tackle Implant-Level Lithography Materials
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/25/2008

Rohm and Haas Electronic Materials has entered into a joint development agreement with IBM to develop patterning materials and processes to enable ion implantation at and below the 32 nm node. More