Semiconductor International : Lithography Report
February 13, 2008
IN THIS EDITION
NEWS
 
» Sematech Achieves Single-Digit EUV Mask Blank Defect Goal
» EUV Research Helps Solve 193 nm Resist Problems
» SPIE and the IC Design World: A Wall Starts Coming Down
» Researchers Develop Forward-Looking Polymer With Immediate Applications
» IMEC, Powerchip Expand Sub-32 nm CMOS Research
» Roadmap Dictated by Flash, More Than Moore
» Albany NanoTech, IMEC to Collaborate on EUV Lithography Research
» Litho Faces Daunting Materials Hurdles
» Cymer Outlook Reflects Advanced Lithography Climate
» ASML Sees Lithography Market Expansion in 2008
» Brion's Tachyon OPC+ Selected by NEC Electronics
» Fujifilm Invests in Lithographic Tool for Resist Development
EDITOR'S PICKS
 
» Take a Survey: Nanoimprint Lithography
» Key Parameters Demonstrated for High-Volume EUV Lithography Sources
» DFM: The Changing Semi Landscape
» Novel CD-SEM Overlay Method Improves Dual Trench Patterning CDU
» Embedded OPC Extends Laser Mask Writers to 65/45 nm
» Double Patterning: An Etch Perspective
» Litho Factions Search for Resources
PRODUCTS
 
» Coat/Develop System
» KrF/ArF Gas Exchange
» SEM/FIB
UPCOMING EVENTS
 
Dear Subscriber,

With the focus on lithography in our February issue and the Advanced Lithography conference barking at our heels, I have a particularly large supply of litho developments to report to you this month. Believe me, these are actually only the highlights, but there's just so much going on that is of interest, including the latest progress in EUV, new perspectives on double patterning and high-index immersion, plus a few other gems. Check out the latest news and technical articles below, then check back regularly at our Lithography Technology Channel to stay up to date:
www.semiconductor.net/lithography

Aaron Hand, Executive Editor, Electronic Media
ahand@reedbusiness.com

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This year's keynote address by: Ben Eynon of Sematech, "EUV Technology: Infrastructure for Success." Feb. 24, 2008. 5:30 p.m. San Jose Marriott.
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NEWS

Sematech Achieves Single-Digit EUV Mask Blank Defect Goal
Business Wire, 2/11/2008

Technologists at Sematech have successfully demonstrated world-class results in low defect density for mask blanks used in extreme ultraviolet (EUV) lithography. More
Read The Fine Print blog

EUV Research Helps Solve 193 nm Resist Problems
Alexander E. Braun, Senior Editor — Semiconductor International, 2/6/2008

Leading-edge research into the requirements for EUV photoresists is helping to solve some of the problems encountered by 193 nm lithography technology as it ventures into increasingly smaller CDs. More

SPIE and the IC Design World: A Wall Starts Coming Down
Ron Wilson, Executive Editor — EDN, 2/11/2008

If you want a graphic indication of how much the wall between SoC design and chip manufacturing has come down, take a look at SPIE Advanced Lithography. For years, this conference has been the premier place where lithography specialists talk to each other about how to make patterns on wafers, but it has been all but unapproachable for chip designers or EDA engineers, unless they happened to have a background in physical optics. But increasingly, and this year may be the inflection point, SPIE has been concerned as well about the impact that lithography is having on the IC design process. Blog

Researchers Develop Forward-Looking Polymer With Immediate Applications
Sally Cole Johnson, Contributing Editor — Semiconductor International, 2/4/2008

A team led by researchers from Rensselaer Polytechnic Institute has developed a polymer that could be used in flip-chip packaging, as well as in nanoimprint lithography. The new polymer, polyset epoxy siloxane (PES), may allow chipmakers to eliminate several steps from their production and packaging processes. More

IMEC, Powerchip Expand Sub-32 nm CMOS Research
Ann Steffora Mutschler, Senior Editor — Electronic News, 1/29/2008

To perform R&D for sub-32 nm memory process generations, IMEC (Leuven, Belgium) and Powerchip Semiconductor Corp. (Hsinchu, Taiwan) will work together within IMEC's advanced lithography program to address immersion, double patterning and EUV lithography challenges. More

Roadmap Dictated by Flash, More Than Moore
Laura Peters, Lead Technical Editor — Semiconductor International, 1/25/2007

The 2007 edition of the International Technology Roadmap for Semiconductors (ITRS) projects the technology targets needed to continue to produce semiconductor devices cost-effectively through the year 2022. A significant new focus is the emphasis on More than Moore, the integration of various types of devices, as is deemed cost-effective, either on the same chip or in the same package. More

Advertisement
Feb. 19: Preparing for High-Volume Immersion Lithography
Broadcast in both English and Japanese, this webcast will look at the most pressing challenges facing immersion lithography and the solutions that are being worked on. Panelists include: Soichi Inoue, Toshiba Semiconductor Co.; Burn Lin, TSMC; Kurt Ronse, IMEC; Bryan Rice, Sematech.
Register Now!

Sponsored by: ASML

Albany NanoTech, IMEC to Collaborate on EUV Lithography Research
Staff — Semiconductor International, 1/22/2008

Albany NanoTech and IMEC will cooperate on EUV lithography research. IBM and ASML researchers will also participate, using the EUV alpha demo tools now being upgraded at both organizations. More

Litho Faces Daunting Materials Hurdles
Alexander E. Braun, Senior Editor — Semiconductor International, 1/18/2008

Bryan Rice, Sematech's immersion lithography program manager, outlined the materials challenges facing high-index immersion lithography, including fluids and lens materials. Speaking at the SEMI Strategic Materials Conference, Rice said a breakthrough in the field of high-index lens materials may come in the next few months. More

Cymer Outlook Reflects Advanced Lithography Climate
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 1/31/2008

Cymer Inc. (San Diego) recently released its quarterly and annual revenue results. Given the company's powerhouse status in providing lightsources for such emerging technologies as immersion lithography, double patterning and extreme ultraviolet (EUV) lithography, it was interesting to hear its executives' perspectives on the marketplace. Although analysts and other company execs are painting a pretty gloomy picture for 2008 capital spending, and the laser system outlook is really no exception, it's interesting to see the potential growth at the leading edge — particularly in the latter half of the year. More

ASML Sees Lithography Market Expansion in 2008
Ann Steffora Mutschler, Senior Editor — Electronic News, 1/16/2008

The litho tool supplier said that within the current sentiment of global economic weakness, underlined by an overall 2008 semiconductor capital investment slowdown forecast by some analysts and customers, it believes it is still well-positioned for robust revenues in the first half of this year. More
Read the transcript of the conference call

Brion's Tachyon OPC+ Selected by NEC Electronics
Business Wire, 1/21/2008

Brion Technologies announced that Japan's NEC Electronics Corp. has placed a significant order for Brion's Tachyon OPC+ optical proximity correction product, which will help to enable NEC's production of next-generation 40 nm ICs. More

Fujifilm Invests in Lithographic Tool for Resist Development
Business Wire, 1/17/2008

Fujifilm Electronic Materials will use the new ArF-based immersion exposure tool to accelerate high-resolution photoresist development for next-generation semiconductors. More

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EDITOR'S PICKS

Take a Survey: Nanoimprint Lithography
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/8/2008

The National Institute of Standards and Technology (NIST, Gaithersburg, Md.) and NIL Technology (Kongens Lyngby, Denmark) are conducting a global survey on nanoimprint lithography. Together, the two organizations are looking to identify the major roadblocks facing the implementation of nanoimprint, looking specifically at the materials and metrology needs. So if you think you might have some input, please take the survey. Blog

Key Parameters Demonstrated for High-Volume EUV Lithography Sources
Nigel Farrar, David Brandt and James Bonafede, Cymer Inc., San Diego — Semiconductor International, 02/01/2008

With extreme ultraviolet (EUV) lithography expected to be the primary high-volume exposure method beyond the 32 nm node, development of a reliable, high-power EUV lightsource remains a key challenge. Our recent results demonstrate power output of 100 W in burst mode. More

DFM: The Changing Semi Landscape
Mark Mason, Chair, Si2 Design for Manufacturability Coalition Director, Design Data Integration, Senior Member Technical Staff (Emeritus), Texas Instruments Inc., Dallas — Semiconductor International, 2/1/2008

In 2003, Chris Mack observed that the semiconductor industry "as we know it" was changing. He argued that the days of non-linear growth and exponential improvements in technology were coming to a close, and that the semiconductor industry was maturing. More

Novel CD-SEM Overlay Method Improves Dual Trench Patterning CDU
Ilan Englard, Rich Piech, Liraz Gershtein, Ram Peltinov and Ofer Adan, Applied Materials Inc., Santa Clara, Calif. — Semiconductor International, 2/1/2008

Using a trench-within-a-trench overlay mark and automated process control strategy, the CD uniformity issue associated with dual trench patterning can be kept within a production-worthy range. More

Embedded OPC Extends Laser Mask Writers to 65/45 nm
Anders Öesterberg, Micronic Laser Systems AB, Täby, Sweden; Steffen Schulze, Mentor Graphics Corp., Wilsonville, Ore. — Semiconductor International, 2/1/2008

Embedded optical proximity correction (OPC) can significantly enhance the CD linearity and proximity performance on photomasks by applying pre-patterning CD corrections to mask pattern data. More

Double Patterning: An Etch Perspective
Raghu Balasubramanian, Andy Romano and Marshall Benham, Lam Research Corp., Fremont, Calif. — Semiconductor International, 2/1/2008

Double patterning requires new critical etches capable of sub-1.5 nm CD uniformity, pattern shrink and in situ full-stack etching. More

Litho Factions Search for Resources
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/1/2008

What lithography techniques will the industry use to mass produce critical layers at 32 nm? Of course, if anybody truly had the answer to that question, they could probably get a little rich. But there seems to be very little in the way of answers. Or rather, perhaps there's too much in the way of answers. More

PRODUCTS

Coat/Develop System

RF3T is a 200 wph coat/develop track system targeted for the full range of lithography applications. The system features additional parallel process modules and higher-efficiency wafer transport.
Sokudo Co. Ltd., Kyoto, Japan
More

KrF/ArF Gas Exchange

The Gas Lifetime eXtension (GLX) product is a standalone upgrade for new and installed systems. It increases chipmakers' scanner output and availability by extending the time between excimer laser gas exchanges by a factor of 10.
Cymer Inc., San Diego
More

SEM/FIB

MultiBeam is a high-throughput SEM/FIB designed for IC defect analysis, circuit modification, TEM thin-film sample preparation and mask repair. It features Slicing and Sampling (S3) for in-process monitoring of milling, fabrication and reconstructing 3-D images of the sectioned area.
JEOL USA, Peabody, Mass.
More

UPCOMING EVENTS

Feb. 19, 2008: Preparing for High-Volume Immersion Lithography

Feb. 24-29, 2008: SPIE Advanced Lithography

March 2-4, 2008: ISS Europe

Copyright 2008 Reed Business Information, a division of Reed Elsevier Inc. All Rights Reserved.
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