Unexpected nFET Gains for 110 Silicon
David Lammers, News Editor — Semiconductor International, 1/14/2008

The future of CMOS may switch from the (100)-oriented crystalline silicon used throughout the semiconductor industry today to (110)-oriented wafers, according to Sematech (Austin, Texas) researcher Rusty Harris. More

Heterogeneous CMOS Gaining Momentum
David Lammers, News Editor — Semiconductor International, 1/10/2008

Research groups are stepping up efforts in heterogeneous semiconductors as a way of extending CMOS, using epitaxial techniques to deposit materials with higher mobilities than silicon. Heterogeneous devices may be formed on silicon wafers, incorporating, for example, germanium in the pFETs and III-V materials in the nFETs, including GaAs, InGaAs or InSb. More

MIRAI Team Studies Threshold Voltage Variation Causes
Kenji Tsuda, Asia Contributing Editor — Semiconductor International, 1/7/2008

With transistor threshold voltage variability now a top-shelf concern, a group of researchers, led by Toshiro Hiramoto, at Japan's Millennium Research for Advanced Information (MIRAI, Tokyo) consortium have studied the role of dopant levels and other factors. More

32 nm Marked by Litho, Transistor Changes
Laura Peters, Lead Technical Editor — Semiconductor International, 1/1/2008

In the logic world, both IBM and Intel announced their intention to use high-k dielectrics and metal gates at the 45 nm node last year. For these stacks, two integration approaches have emerged: gate-first, where, in a similar manner to existing poly/SiON gates, the gate is subjected to thermal cycles including the high-temperature junction anneals; and gate-last, where a dummy poly gate undergoes heat cycles and subsequent processes, then the dummy gate is removed and replaced with a high-k/metal gate stack (replacement gate approach). More

1 THz InP Transistor Claims Speed Record
Peter Singer, Editor-in-Chief — Semiconductor International, 12/21/2007

Northrop Grumman Corp. (Redondo Beach, Calif.) is claiming a new world record for transistor speed with an indium phosphide-based high-electron-mobility transistor (InP HEMT). The device has a maximum frequency of operation of >1 THz (1000 GHz). Researchers at Northrop Grumman's Space Technology sector, led by Richard Lai, detailed how they developed the terahertz-speed transistor in a technical paper delivered at the 2007 International Electron Devices Meeting (IEDM), held last month in Washington, D.C. More

Toshiba Joins IBM Alliance for 32 nm Bulk Process Development
David Lammers, News Editor — Semiconductor International, 12/18/2007

IBM Corp. (Armonk, N.Y.) and Toshiba Corp. (Tokyo) announced that they have extended their relationship at the IBM-led process development alliance, entering into a joint development agreement on 32 nm bulk CMOS process technology. The work will be conducted as part of the now seven-company alliance, based in East Fishkill, N.Y. More

NEC Develops Channel-Engineering Technique
JCN Newswire, 12/13/2007

NEC Corp. and NEC Electronics Corp. have successfully developed design technology to realize optimum channel structure in CMOS transistors for advanced LSIs in the 32 nm generation and beyond. This achievement relies on visualization of impurity distributions in transistors based on electron-beam holography technology with high spatial resolution. More

SRC, University of Glasgow Aim for 8 nm Node Chips
Business Wire, 12/12/2007

The Semiconductor Research Corp. (SRC) announced that the University of Glasgow (Scotland) will help identify the best p channel material to scale the MOSFET minimum feature size, including gate length, down to the 8 nm technology generation. Exploiting compound semiconductor materials, progress expected from the Glasgow research will enable scaling of faster silicon chips for an additional 4-6 years beyond previous projections. More