45 to 32 nm: Another Evolutionary Transition
Laura Peters, Lead Technical Editor — Semiconductor International, 1/1/2007

Those expecting more revolutionary changes at the 32 nm node may be disappointed by the evolutionary changes in process technology that still allow performance specifications of the latest devices to be met. Still, there are a few notable exceptions. More

Intel and IBM Commit to High-k, Metal Gates
Peter Singer, Editor-in-Chief — Semiconductor International, 1/29/2007

In a surprise announcement described as the "biggest change to computer chips in 40 years," Intel said it has committed to putting hafnium-based high-k gate dielectrics and metal gate electrodes into production for the 45 nm generation. Intel's announcement was quickly followed by a similar one from IBM. More

3-D Through-Silicon Vias Become a Reality
Jan Vardaman, TechSearch International, Austin, Texas — Semiconductor International, 6/1/2007

One of the hottest topics in the semiconductor industry today is 3-D with through-silicon via (TSV) technology. While many research programs have been underway for years, commercial products have yet to be introduced. What is driving the market for this new technology? What materials and processes will be used? Will vias be formed during the wafer fabrication process or during IC packaging and assembly? More

High-k/Metal Gates Prepare for High-Volume Manufacturing
Reza Arghavani, Gary Miner and Melody Agustin, Applied Materials Inc., Santa Clara, Calif. — Semiconductor International, 11/1/2007

At the 45 nm node, high-k dielectrics and metal gates will be used in logic devices. Flash memory can also benefit from this new technology, taking advantage of high metal workfunctions and bandgap-engineered charge-trap memories. More

Who Is Building and Will Build 300 mm Fabs?
George Burns, Strategic Marketing Associates, Santa Cruz, Calif. — Semiconductor International, 12/1/2006

The first 300 mm pilot line (Semiconductor 300) began production as a joint venture between Siemens and Motorola in 1999 in Dresden, Germany. What started as one single fab less than 10 years ago has now become an avalanche. By the end of this year, there will be as many as 70 300 mm fabs online. More

Bulk or SOI? AMD Considering Its Options
David Lammers, News Editor — Semiconductor International, 7/31/2007

Advanced Micro Devices (AMD, Sunnyvale, Calif.) is still mulling whether to use silicon on insulator (SOI) or bulk silicon technology for its future high-end and mobile products. More

NBTI: A Growing Threat to Device Reliability
Laura Peters, Lead Technical Editor — Semiconductor International, 3/1/2004

Negative bias temperature instability (NBTI) is a very real issue for sub-130 nm CMOS devices because of its deleterious effect on threshold voltage and drive current. Through better modeling of actual device behavior and better understanding of the NBTI threat with continued device scaling, engineers can minimize the impact of NBTI on future devices. More

Enabling 3-D Design
Arthur Keigler, Kathy O'Donnell, Zhenqiu Liu and Bill Wu, NEXX Systems, Billerica, Mass.; John Trezza, Cubic Wafer, Austin, Texas — Semiconductor International, 8/1/2007

An IC with stacked memory shows a 1000-fold increase in speed with a 100-fold decrease in power consumption. More

Nanotechnology: Turning Nanoscience Into Nanomanufacturing
Peter Singer, Editor-in-Chief — Semiconductor International, 1/1/2007

Despite nanotechnology's incredible promise, it will likely be 5-10 years before nanostructures, such as carbon nanotubes and nanowires, become a staple of mainstream manufacturing. More

Applied's Solar Strategy Goes Very Large
David Lammers, News Editor — Semiconductor International, 11/20/2007

Applied Materials Inc.'s decision to buy Baccini SpA (Treviso, Italy) for $330M expands Applied's capabilities in the crystalline silicon (c-Si) portion of the photovoltaic (PV) industry. While the c-Si market is growing as more businesses and homeowners seek to connect rooftop solar panels to the electrical power grid, Applied CEO Michael Splinter has his sights set on the larger prize: thin-film PV modules. More

The Potential of Thin-Film Crystalline Silicon Solar Cells
Koen Snoeckx, Guy Beaucarne, Filip Duerinckx, Ivan Gordon and Jef Poortmans, IMEC, Leuven, Belgium — Semiconductor International, 6/1/2007

If the efficiency and cost targets can be met, thin-film crystalline silicon solar cells have the potential to become a solid alternative to the bulk multicrystalline silicon solar cells that currently dominate the photovoltaics market. More

Strained Silicon: Essential for 45 nm
Laura Peters, Lead Technical Editor — Semiconductor International, 3/1/2007

Silicon stressor techniques can be combined to provide cost-effective, low-risk ways of delivering next-node mobility improvements and drive currents. More

Webcast: Strained Silicon Update
Moderated by Laura Peters, Lead Technical Editor — Semiconductor International, 3/13/2007

Implementing strain in silicon is a fairly straightforward means of inducing higher carrier mobility in devices (electrons in NMOS, holes in PMOS), leading to transistors with higher drive currents. This webcast explores the various means used to induce stress in silicon, and discusses the advantages of combining the different approaches. Industry experts also talk about the extendibility of different stressor techniques to future device generations. View

Si and Ge Solar Cell Efficiency Records Set
Peter Singer, Editor-in-Chief — Semiconductor International, 10/11/2007

It was announced at SEMICON Europa that new records for thin-wafer silicon and germanium solar cells were set by IMEC (Leuven, Belgium). The research consortium realized an impressive efficiency of 17.4% for its thin-wafer silicon solar cells realized with its industrial passivated emitter and rear cells (i-PERC) process. More

AMD Building Advanced Development Center
David Lammers, News Editor, and Peter Singer, Editor-in-Chief — Semiconductor International, 10/24/2007

As part of its emphasis on small-batch processing and lean manufacturing, Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.) is building an advanced development center in Austin, Texas, that is expected to be in operation early next year. During a keynote speech at the International Sematech Manufacturing Initiative (ISMI) Symposium, Doug Grose, senior vice president in charge of manufacturing and supply chain at AMD, made brief reference to the development center, saying it was part of AMD's emphasis on reduced cycle times, improved tool predictability and "mini batch tools." More

Blog: Semi-Conscious
Peter Singer, Editor-in-Chief — Semiconductor International

Launched in July 2007, Pete's blog has reflected on the discovery of the transistor 60 years ago, how realistic a 450 mm wafer transition might be, and whether or not process technology is becoming a commodity, among other controversial topics. Blog

Webcast: 3-D Integration: What Direction Will It Take?
Moderated by Laura Peters, Lead Technical Editor — Semiconductor International, 9/5/2007

Imagine a 1000x improvement in speed and 100x improvement in power. That's the incredible promise of 3-D integration, which involves thinning the wafer or die and then stacking and electrically connecting them. One challenge is that there are many different ways to accomplish 3-D integration, each with different cost implications. During this webcast, panelists look at the devices driving 3-D integration approaches. View

Double Patterning Wrings More From Immersion Lithography
Aaron Hand, Executive Editor, Electronic Media — Semiconductor International, 2/1/2007

With high-index immersion looking less hopeful than some may have hoped, the industry is abuzz with talk about double patterning as the sledgehammer approach to extending water-based optical lithography. More

Wafer Cleaning and Surface Prep: Evolution to Revolution
Peter Singer, Editor-in-Chief — Semiconductor International, 4/1/2007

Most cleaning challenges are evolutionary as structures get smaller and specs get tighter, but a revolution is in the making, brought on by a variety of new materials, new integration schemes and process flows. More

Intel Takes 45 nm High-k/Metal Gate Process to IEDM
David Lammers, News Editor — Semiconductor International, 12/14/2007

Intel Corp. (Santa Clara, Calif.) provided some details of its 45 nm high-k/metal gate process flow at the International Electron Devices Meeting (IEDM) in Washington, D.C., although key elements of the pFET electrode metal remained shrouded. Kaizad Mistry, vice president of logic integration, said Intel used a "high-k first, metal gate last" approach. More