The latest news and information on major semiconductor manufacturing process steps, including etch, deposition, epitaxy, chemical mechanical planarization (CMP) and thermal processing.
Lanthanum Doping May Boost Silicon FETs David Lammers, News Editor - 12/30/2008
Experts at the recent IEDM said performance gains from strained silicon are saturating, causing Sematech researchers to look at adding lanthanum to the gate dielectric and growing a thin epitaxial layer of germanium in the silicon channel. “We don’t have that much room left in silicon,” warned MIT Professor Dimitri Antoniadis. More
Elpida in Talks With Taiwan DRAM Makers David Lammers, News Editor - 12/29/2008
Japan’s Elpida Memory is discussing a possible four-way merger that would combine it with Taiwan’s Powerchip, ProMOS and the Rexchip Electronics joint venture. The talks come shortly after separate refinancing deals were arranged for Hynix Semiconductor in South Korea and Qimonda in Germany. Qimonda is betting on a new stacked capacitor DRAM design that was described at the recent IEDM conference.
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Flash Vendors Facing Scaling Challenges David Lammers, News Editor - 12/23/2008
Toshiba engineers said at the recent IEDM that they have improved on the SONOS flash structure, creating a double-tunnel oxide structure that can extend flash to the 10 nm generation. Also at IEDM, flash pioneer Stefan Lai said he believes phase-change memories have the best chance to replace today’s floating gate memories. Lai said he “made a bad call” while at Intel in the late 1980s, rejecting NAND flash as unreliable.
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Leading-Edge Logic Processes Presented at IEDM Session David Lammers, News Editor - 12/18/2008
AMD, IBM and its Fishkill Alliance partners, Intel, an NEC-Toshiba collaborative effort and TSMC all presented leading-edge logic processes at 45, 32 and 22 nm design rules at the International Electron Devices Meeting (IEDM). Although several of the processes are not expected to go into production in the form presented this week, Intel said during a late paper presentation that it has completed the process development phase of its 32 nm process.
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How Intel Made CMP Work for High-k Laura Peters, Editor-in-Chief - 12/18/2008
Joe Steigerwald, director of CMP technology at Intel, described the CMP process improvements necessary for replacement metal gate (RMG) processing. “Gate height control was the area where we struggled the most,” he said in an invited speech at the International Electron Devices Meeting (IEDM) in San Francisco. Reducing defectivity levels was another challenge. He called on pad and slurry suppliers to speed up their development cycles.
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IEDM Panel: Processing Costs Headed Up David Lammers, News Editor - 12/17/2008
With more expensive tools and new process modules coming, IC manufacturers will struggle to maintain the cost-per-function reductions that have broadened the market for semiconductors. The likely introduction of 3-D interconnects, vertical transistors and EUV lithography all will add pressure on wafer processing costs, experts said at an evening panel discussion at the International Electron Devices Meeting going on in San Francisco this week.
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Intel Sees PMOS Gain With (110) Silicon David Lammers, News Editor - 12/16/2008
At the 2008 International Electron Devices Meeting (IEDM), speakers from Intel and Fujitsu outlined (110) silicon research that shows significant improvement to the PMOS transistors. “The use of (110) silicon substrates is a promising technology option,” said Intel’s Paul Packan. Intel created 45 nm transistors on (110) wafers and achieved what Packan said was record PMOS drive current.
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Multigate FETs: A Risky Proposition Laura Peters, Editor-in-Chief - 12/15/2008
After years of R&D, multi-gate devices (MuGFETs) with vertical structures still fall into the “high risk” category, according to Intel Fellow Kelin Kuhn, who assessed the risks of 22 nm options during a presentation at IEDM on Sunday. Challenges with parasitic resistance, parasitic capacitance and topology will make vertical devices difficult to implement. Strain techniques, so successful with planar transistors, may not work as well, she said.
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Views on News David Lammers, News Editor, Semiconductor International December 10, 2008 Mark Bohr and the Drive Current Debate
It's IEDM time, and tis the season for Intel and IBM to throw snowballs at the compet... More
Views on News David Lammers, News Editor, Semiconductor International October 6, 2008 IBM And The All-In Bet on High-K
The debate about the worthiness of high-k/metal gate technology brought to mind what ... More
Views on News David Lammers, News Editor, Semiconductor International June 27, 2008 IBM@45: eDRAM, Si! High-k, No
It now appears that IBM Corp. plans to implement a high-bandwidth silicon-on-insulato... More
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Technical Articles
Laser Spike Annealing Improves Leading-Edge Devices Y. Wang, J. Hebb, D. Owen and A.M. Hawryluk, Ultratech Inc., San Jose, 12/01/2008
Millisecond and microsecond laser spike anneal improves logic and memory device performance. Shrinking thermal budgets will require a shorter anneal process, with dwell times under 400 µsec....
CoO Dictates Memory's Move to Copper Tom Caulfield, Executive Vice President, Sales, Marketing and Customer Service, Novellus Systems Inc., San Jose, www.novellus.com, 12/01/2008 Ten years after its initial introduction for logic device manufacturing, copper interconnect technology is rapidly being adopted for memory chip production. For advanced nodes, the technical advantages of a copper metallization scheme over an aluminum interconnect have long been recognized....
Measuring Material, Dopant Loss From Post-Implant Wafer Cleans Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif., 11/01/2008
Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes....
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Laser Spike Annealing Improves Leading-Edge Devices
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