The latest news and information on major semiconductor manufacturing process steps, including etch, deposition, epitaxy, chemical mechanical planarization (CMP) and thermal processing.
Physical Analysis Provides Images of 45 nm Laura Peters, Editor-in-Chief - 05/06/2008
Engineers at Chipworks Inc. (Ottawa, Canada) have uncovered many physical details of the 65 and 45 nm process technologies. More
Splinter Sees Weak Order Period Looming for Equipment Vendors David Lammers, News Editor - 05/13/2008
Applied Materials CEO Michael Splinter said the third fiscal quarter may see silicon equipment sales drop by 40% from the second fiscal quarter ending April 27, representing the bottom of the current downcycle. Orders from flash vendors in particular have been less than expected. One bright spot was introduction of the Aera2 mask inspection system, which is being used by four customers now, he said.
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Applied Tackles Edge With Inflexion Polishing System David Lammers, News Editor, and Laura Peters, Editor-in-Chief - 05/07/2008
Applied Materials introduced the Inflexion edge polishing system that has an integrated wafer cleaning capability. The Inflexion tool uses abrasive tape to clean the wafer’s edge, an area that faces new contamination issues as immersion lithography pushes liquids to the edge of the wafer.
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Self-Aligned Barrier Improves Interconnect Reliability H.J. Wu, J. O'loughlin, R. Shaviv, M. Sriram, K. Chattopadhyay, Y. Yu, T. Mountsier, B. van Schravendijk, S. Varadarajan, G. Dixit and R. Havemann, Novellus Systems Inc., San Jose - 05/01/2008
A new PECVD self-aligned barrier using a germanium dopant offers a simple, cost-effective means of improving electromigration resistance of copper interconnects.
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Advanced Metallization Needs Integrate Copper Into Memory Niranjan Kumar, Kevin Moraes, Murali Narasimhan and Prabu Gopalraja, Applied Materials Inc., Santa Clara, Calif. - 05/01/2008
Logic interconnect technology has been driven by dual-damascene feature scaling, low-k integration and copper interconnect reliability performance requirements. With memory devices going from aluminum to copper, requirements such as gap-fill extendibility are more challenging.
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Real Men/Women Do Have Fabs Laura Peters, Editor-in-Chief - 04/30/2008
Tom Sonderman, vice president of manufacturing technology at Advanced Micro Devices (AMD, Sunnyvale, Calif.), declared at yesterday’s SEMI Strategic Business Conference (Napa Valley, Calif.) that “real men and women do have fabs.”
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TSMC Ramping Aggressive CPU Process Push David Lammers, News Editor - 04/29/2008
TSMC is “hiring aggressively” to develop a technology platform for CPU production, said CEO Rick Tsai. While conceding that TSMC’s process technology has lagged Intel’s thus far, Tsai said TSMC expects its processor production to “blossom” starting in 2010.
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TSMC Sketches 32 nm Rollout Plan for 2009 David Lammers, News Editor - 04/28/2008
Taiwan Semiconductor Manufacturing Co. Ltd. plans to begin 32 nm production in the third quarter of 2009, with foundry production of dual core 3G cell phone chipsets as one focus, said Jack Sun, TSMC’s vice president of R&D. TSMC will use a high-k/metal gate process for high-frequency microprocessor production, he said, while sticking with a poly/oxynitrides gate stack for the general purpose and low-power platforms.
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Dan Herr is director of Nanomanufacturing Science Research at SRC. An important part of his research focuses on nanotechnology’s demands on metrology, and he discusses his work to determine where metrology technology’s gaps are, and how to fill them.
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Technical Articles
Self-Aligned Barrier Improves Interconnect Reliability H.J. Wu, J. O'loughlin, R. Shaviv, M. Sriram, K. Chattopadhyay, Y. Yu, T. Mountsier, B. van Schravendijk, S. Varadarajan, G. Dixit and R. Havemann, Novellus Systems Inc., San Jose, 05/01/2008
A new PECVD self-aligned barrier using a germanium dopant offers a simple, cost-effective means of improving electromigration resistance of copper interconnects....
Advanced Metallization Needs Integrate Copper Into Memory Niranjan Kumar, Kevin Moraes, Murali Narasimhan and Prabu Gopalraja, Applied Materials Inc., Santa Clara, Calif., 05/01/2008
Logic interconnect technology has been driven by dual-damascene feature scaling, low-k integration and copper interconnect reliability performance requirements. With memory devices going from aluminum to copper, requirements such as gap-fill extendibility are more challenging....
Improving Electrical Performance Using SACVD Oxide Films Cary Ching, Harry Whitesell and Shankar Venkataraman, Applied Materials Inc., Santa Clara, Calif., 04/01/2008
An O3/TEOS-based sub-atmospheric CVD process demonstrates improved drive current, junction leakage and superior gap fill for aspect ratios >8:1 for STI and >6:1 for PMD. Use in a locally strained channel device is also demonstrated....
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Self-Aligned Barrier Improves Interconnect Reliability
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