The latest news and information on semiconductor materials, including silicon wafers, compound semiconductors, low-k and high-k dielectrics, metal gates, copper, silicon on insulator (SOI), and strained silicon.
Flash Vendors Facing Scaling Challenges David Lammers, News Editor - 12/23/2008
Toshiba engineers said at the recent IEDM that they have improved on the SONOS flash structure, creating a double-tunnel oxide structure that can extend flash to the 10 nm generation. Also at IEDM, flash pioneer Stefan Lai said he believes phase-change memories have the best chance to replace today’s floating gate memories. Lai said he “made a bad call” while at Intel in the late 1980s, rejecting NAND flash as unreliable. More
IITC Set for Sapporo in June, Europe in 2011 Staff - 01/08/2009
The International Interconnect Technology Conference (IITC) will move from its traditional venue near the San Francisco airport to Sapporo, Japan, in early June. The conference will focus on 3-D technologies, packaging and system integration, novel materials and interconnect systems, and environmental issues, among others.
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Carbone Lorraine Acquires Calcarb in Solar Push Staff - 12/31/2008
Carbone Lorraine has acquired Calcarb, a manufacturer of rigid graphite felt used as insulation in high-temperature furnaces used by the semiconductor and solar industries.
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Lanthanum Doping May Boost Silicon FETs David Lammers, News Editor - 12/30/2008
Experts at the recent IEDM said performance gains from strained silicon are saturating, causing Sematech researchers to look at adding lanthanum to the gate dielectric and growing a thin epitaxial layer of germanium in the silicon channel. “We don’t have that much room left in silicon,” warned MIT Professor Dimitri Antoniadis.
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How Intel Made CMP Work for High-k Laura Peters, Editor-in-Chief - 12/18/2008
Joe Steigerwald, director of CMP technology at Intel, described the CMP process improvements necessary for replacement metal gate (RMG) processing. “Gate height control was the area where we struggled the most,” he said in an invited speech at the International Electron Devices Meeting (IEDM) in San Francisco. Reducing defectivity levels was another challenge. He called on pad and slurry suppliers to speed up their development cycles.
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Intel Sees PMOS Gain With (110) Silicon David Lammers, News Editor - 12/16/2008
At the 2008 International Electron Devices Meeting (IEDM), speakers from Intel and Fujitsu outlined (110) silicon research that shows significant improvement to the PMOS transistors. “The use of (110) silicon substrates is a promising technology option,” said Intel’s Paul Packan. Intel created 45 nm transistors on (110) wafers and achieved what Packan said was record PMOS drive current.
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Intel to Describe 32 nm Logic Process, New 45 nm SoC Platform, at 2008 IEDM David Lammers, News Editor - 12/10/2008
Intel will provide some details of its 32 nm logic process in a late paper at next week’s IEDM. Intel says drive currents improve by 14% compared with the 45 nm process. Also, Intel will unveil a 45 nm SoC process optimized for low leakage, and promising research on using (110) oriented silicon.
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ATMI and Ovonyx Bring MOCVD to PCMs David Lammers, News Editor - 12/09/2008
ATMI and Ovonyx said they have demonstrated the ability to use MOCVD to fill high-aspect-ratio holes in phase-change memories (PCMs). The PCM devices demonstrated endurance >106 write-erase cycles, an order of magnitude higher than conventional flash. ATMI identified a precursor for the GST material used to fill the holes, and developed a delivery system from the storage container to the process chamber.
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Views on News David Lammers, News Editor, Semiconductor International November 7, 2008 Big Wafers, Big Prices
Dean Freeman, the Gartner semiconductor equipment analyst, threw out a zinger when he... More
Views on News David Lammers, News Editor, Semiconductor International October 31, 2008 Three Innovations to Watch
Innovation is the fourth great economic input, along with labor, capital, and machine... More
Views on News David Lammers, News Editor, Semiconductor International October 23, 2008 When Is No Really a No?
An executive at a major IC manufacturer likes to tell the story about a meeting in 19... More
Views on News David Lammers, News Editor, Semiconductor International October 6, 2008 IBM And The All-In Bet on High-K
The debate about the worthiness of high-k/metal gate technology brought to mind what ... More
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Technical Articles
CoO Dictates Memory's Move to Copper Tom Caulfield, Executive Vice President, Sales, Marketing and Customer Service, Novellus Systems Inc., San Jose, www.novellus.com, 12/01/2008 Ten years after its initial introduction for logic device manufacturing, copper interconnect technology is rapidly being adopted for memory chip production. For advanced nodes, the technical advantages of a copper metallization scheme over an aluminum interconnect have long been recognized....
Optimize Wafer Thickness for 450 mm Tadashi Kanda, Toshiyuki Fujiwara and Kazushige Takaishi, SUMCO Corp., Tokyo, 12/01/2008
Wafer thickness significantly affects costs and yield in wafer and device manufacturing. To avoid the problems experienced at 300 mm, the optimum thickness for 450 mm must be targeted. In this article scheduled to run in Semiconductor International's December print issue, SUMCO (Tokyo) authors share the results of tests they've conducted on sag, support, vibrational effects and more....
Light on the Road to Low-k Integration Youssef Travaly and Mikhail Baklanov, IMEC, Leuven, Belgium, 11/01/2008
Combining greater understanding with new chemistries and integration schemes may help ease the burden of increased porosity and process-induced damage to ultralow-k films....
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CoO Dictates Memory's Move to Copper
