The latest news and information on semiconductor materials, including silicon wafers, compound semiconductors, low-k and high-k dielectrics, metal gates, copper, silicon on insulator (SOI), and strained silicon.
December Sneak Peek: Optimize Wafer Thickness for 450 mm Tadashi Kanda, Toshiyuki Fujiwara and Kazushige Takaishi, SUMCO Corp., Tokyo - 11/24/2008
Wafer thickness significantly affects costs and yield in wafer and device manufacturing. To avoid the problems experienced at 300 mm, the optimum thickness for 450 mm must be targeted. In this article scheduled to run in Semiconductor International's December print issue, SUMCO (Tokyo) authors share the results of tests they've conducted on sag, support, vibrational effects and more. More
IBM Offers 45 nm SOI Foundry Solution David Lammers, News Editor - 11/10/2008
IBM is offering a 45 nm SOI foundry solution to customers seeking to reduce active power consumption. ARM developed an SOI standard cell library, in conjunction with SOI wafer vendor Soitec, that eases SOI designs. Chartered will provide a second-source foundry capability for high-volume SOI customers.
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Light on the Road to Low-k Integration Youssef Travaly and Mikhail Baklanov, IMEC, Leuven, Belgium - 11/01/2008
Combining greater understanding with new chemistries and integration schemes may help ease the burden of increased porosity and process-induced damage to ultralow-k films.
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Can We Afford High-k for III-Vs? David Lammers, News Editor - 11/01/2008 It is getting harder to wring performance gains from silicon, even as the transistor size is made smaller. That trend leads to an intensifying debate about whether III-V transistors will augment silicon in performance-driven applications.More
Magnetism and Nanocrystals Promise Denser Storage, New Devices Alexander E. Braun, Senior Editor - 10/30/2008
When complex materials are reduced to the nanoscopic scale, never before observed electronic transport phenomena can be seen. Researchers at Oak Ridge National Laboratory are striving to gain a fuller understanding of the mechanisms at play, which could lead to new device applications in spin valves, MRAM or photovoltaics.
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Logic Technologies Face Off at IEDM David Lammers, News Editor - 10/28/2008
At the International Electron Devices Meeting (IEDM) planned for Dec. 15-17 in San Francisco, IBM and its partners AMD and Freescale will present a thin SOI technology used to create a 22 nm functional SRAM with a cell size of 0.1 µm2. Intel researchers will detail their 32 nm logic platform, which delivers drive currents of 1.55 mA/µm for the NMOS and 1.21 mA/µm for the PMOS transistors.
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ISMI Outlines 450 mm Wafer, NGF Roadmaps David Lammers, News Editor - 10/27/2008
ISMI managers described progress at the 450 mm wafer Interoperability Test Bed, and described the Phase 2 roadmap at last week’s ISMI Symposium on Manufacturing Effectiveness. Also, the Next Generation Factory program at ISMI is continuing work on cycle time improvements for existing and greenfield 300 mm wafer fabs, including support for 12-wafer lots.
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Views on News David Lammers, News Editor, Semiconductor International November 7, 2008 Big Wafers, Big Prices
Dean Freeman, the Gartner semiconductor equipment analyst, threw out a zinger when he... More
Views on News David Lammers, News Editor, Semiconductor International October 31, 2008 Three Innovations to Watch
Innovation is the fourth great economic input, along with labor, capital, and machine... More
Views on News David Lammers, News Editor, Semiconductor International October 23, 2008 When Is No Really a No?
An executive at a major IC manufacturer likes to tell the story about a meeting in 19... More
Views on News David Lammers, News Editor, Semiconductor International October 6, 2008 IBM And The All-In Bet on High-K
The debate about the worthiness of high-k/metal gate technology brought to mind what ... More
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Technical Articles
December Sneak Peek: Optimize Wafer Thickness for 450 mm Tadashi Kanda, Toshiyuki Fujiwara and Kazushige Takaishi, SUMCO Corp., Tokyo, 11/24/2008
Wafer thickness significantly affects costs and yield in wafer and device manufacturing. To avoid the problems experienced at 300 mm, the optimum thickness for 450 mm must be targeted. In this article scheduled to run in Semiconductor International's December print issue, SUMCO (Tokyo) authors share the results of tests they've conducted on sag, support, vibrational effects and more....
Light on the Road to Low-k Integration Youssef Travaly and Mikhail Baklanov, IMEC, Leuven, Belgium, 11/01/2008
Combining greater understanding with new chemistries and integration schemes may help ease the burden of increased porosity and process-induced damage to ultralow-k films....
Can We Afford High-k for III-Vs? David Lammers, News Editor, 11/01/2008 It is getting harder to wring performance gains from silicon, even as the transistor size is made smaller. That trend leads to an intensifying debate about whether III-V transistors will augment silicon in performance-driven applications....
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December Sneak Peek: Optimize Wafer Thickness for 450 mm
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