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The latest news and information on semiconductor clean processing, including wafer cleaning; photoresist stripping; cleanrooms; environment, safety and health; and contamination control.

  • FSI Enters Single-Wafer Clean Market
    Aaron Hand, Executive Editor, Electronic Media - 11/03/2008
    FSI International (Chaska, Minn.) has made its single-wafer debut with its Orion cleaning system, which enables advanced wafer cleaning capabilities for such critical device structures as ultrashallow junctions, high-k/metal gates and metal capping layers. Innovative spray-bar and closed-chamber designs improve on competing single-wafer platforms, according to FSI’s Scott Becker. More

  • Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
    Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif. - 11/01/2008
    Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes. More
  • Environmental Regulations Growing More Complex
    David Lammers, News Editor - 10/22/2008
    Participants at an ISMI meeting on emerging environment, safety and health (ESH) regulations said the Stockholm Convention on Persistent Organic Pollutants is expected to vote on a ban of PFOS in May. The possible ban is part of an increasingly complex set of environmental regulations, with China taking an ever-dimmer view of potential contaminants. More
  • IMEC Views 3-D Stacking as System Design
    Laura Peters, Editor-in-Chief - 10/14/2008
    IMEC managers said the research center has made significant progress creating test 3-D ICs, using die-to-die stacking. IMEC’s Eric Beyne said achieving coplanar and particle-free surfaces still presents processing challenges. He described the dual-damascene via processing as comparable to traditional front-end interconnect via processing, but with larger features. More
  • How Pump-Induced Particles Affect Low-k CMP Defectivity
    F.C. Chang, S. Tanawade and Rajiv Singh, Dept. of Materials Science and Engineering and Particle Engineering Research Center, University of Florida, Gainesville, Fla. - 09/01/2008
    High shear flow generated by positive displacement pumps increases the distribution of oversized particles, leading to significantly increased wafer surface defectivity (scratches or roughness) during CMP, whereas less defectivity was found in slurries circulated by a magnetically levitated (maglev) centrifugal pump. More
  • Treating Copper CMP Wastewater
    Benjamin Roberts, Dean Novy and Chris Jones, Edwards, Wilmington, Mass.; Paul Tan, Jimmy Wang and Chris Lou, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Hsinchu, Taiwan - 09/01/2008
    Waste rinses from an actual copper CMP process in a fab were treated using an ion exchange system. Optimization took place around column flow rate, resin type and post-treatment flocculation agents. More
  • Shin-Etsu Polymer Develops Lightweight Resin Frame for Thin Wafers
    Kenji Tsuda, Asia Contributing Editor - 08/06/2008
    Shin-Etsu Polymer has developed a lightweight resin frame to handle and transport thinned wafers. The resin frame would replace the conventional stainless steel frames that tend to produce metallic contamination during wafer handling. Thinned wafers are increasingly being used for chips that have 3-D interconnects and ultrathin packages. More
  • Resist Removal Walks a Tightrope
    Ruth DeJule, Contributing Editor - 08/01/2008
    Between limiting damage to low-k materials and silicon removal at the gate, while definitely clearing away all photoresist and its residues, resist removal processes — wet and dry — continue to strive to maintain the right balance. More
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    Measuring Material, Dopant Loss From Post-Implant Wafer Cleans
Nikki Edleman, IBM Microelectronics, Hopewell Junction, N.Y.; Yong-Siang Tan, Chartered Semiconductor Mfg. Ltd., Singapore; Tom Tillery, Stephen Savas, Andreas Kadavanich and Allan Wiesnoski, Mattson Technology, Fremont, Calif., 11/01/2008
Maintaining the integrity of ultrashallow junctions (USJs) after exposure to an increasingnumber of high-dose implant resist cleaning steps is critical for logic device manufacturing at the 45 nm node and beyond. Use of SiGe in the PMOS regions adds an additional material challenge. A new short loop method provides accurate relative measurements of amorphized silicon or SiGe loss caused by different types of strip/clean processes....

    How Pump-Induced Particles Affect Low-k CMP Defectivity
F.C. Chang, S. Tanawade and Rajiv Singh, Dept. of Materials Science and Engineering and Particle Engineering Research Center, University of Florida, Gainesville, Fla., 09/01/2008
High shear flow generated by positive displacement pumps increases the distribution of oversized particles, leading to significantly increased wafer surface defectivity (scratches or roughness) during CMP, whereas less defectivity was found in slurries circulated by a magnetically levitated (maglev) centrifugal pump....

    Treating Copper CMP Wastewater
Benjamin Roberts, Dean Novy and Chris Jones, Edwards, Wilmington, Mass.; Paul Tan, Jimmy Wang and Chris Lou, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Hsinchu, Taiwan, 09/01/2008
Waste rinses from an actual copper CMP process in a fab were treated using an ion exchange system. Optimization took place around column flow rate, resin type and post-treatment flocculation agents....

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