The latest news and information on semiconductor yield management, including process control, reliability, defect detection and design for manufacturing.
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CyberOptics Founder Steven Case Killed in Plane Crash
Staff, June 17, 2009CyberOptics said its chairman and founder Steven Case died Tuesday night when the small plane he was flying crashed. Case founded the company, which makes yield improvement sensors, 25 years ago. More -
Komatsu Laser Marks on Silicon Surface
Kenji Tsuda, Asia Contributing Editor, June 2, 2009
Komatsu Engineering Corp. said it has developed a laser marker that can better identify silicon-based ICs used in applications where chip identification is important, including automotive, medical and computer equipment. The laser irradiates a small portion of the chip, creating a concave surface that forms a 16×16 dot surface. More
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Control Strategy for Wafer-Edge Defects
M.F. Hsu and J.H. Yang, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Hsinchu, Taiwan; E. Yang, H. Chen, M. Ng, M. Li and C. Perry-Sullivan, KLA-Tencor Corp., Milpitas, Calif., June 1, 2009Identifying and resolving systematic process issues on edge die before they migrate to interior die prevents production yield loss and enables faster yield ramp. More -
Everspin MRAM Cited for Zero Defects
Staff, May 18, 2009Everspin Technologies, a venture-backed MRAM manufacturer that spun out of Freescale last year, said it has passed reliability tests at a key customer. Siemens said its touch-screen interface panels have seen zero defects after two years in ~100,000 units. The MRAMs provide nonvolatile storage, replacing battery-backed SRAMs. More -
Mentor Enhancing Yield Diagnostics Tool
David Lammers, News Editor, May 6, 2009
Mentor Graphics is adding more powerful statistical analysis techniques to its yield diagnostics tool, Yield Assist. The technique can narrow down problem areas on the die, and shorten the time required for failure analysis. More
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IMEC Sends Memory DFM Tool to Samsung Electronics
Staff, April 21, 2009IMEC has transferred its Memory Variability Aware Modeling tool to Samsung Electronics. The design-for-manufacturing (DFM) tool predicts yield loss of SRAMs caused by the process variations of deep-submicron IC technologies. More -
IDMs, Fabless Face Reliability Challenges
David Lammers, News Editor, April 15, 2009
Managers from Broadcom, Intel and Xilinx are among the invited speakers at the upcoming International Reliability Physics Symposium. The varying approaches to reliability by the large IDMs and the major fabless vendors that rely on foundries is a theme at this year’s IRPS, scheduled for April 26-30 in Montreal. More
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3-D Equals Two Generations of Scaling
Philip Garrou, Microelectronics Consultants of North Carolina, Research Triangle Park, N.C., April 2, 2009
North Carolina State Professor Paul Franzon said the need for 3-D ICs is becoming more acute as CMOS scaling improvements (according to MIT projections) halt at the 32 nm node and beyond. However, 3-D yield and design challenges remain, according to IBM and Cadence technologists who participated in a IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas. More
News from the Web
Triple-Current-Modulation Delta VBE Thermometry Cancels Ohmic Error Sources
Source: electronicdesign.com
Date: 8 hours 9 minutes 5 seconds ago.Synopsys, TSMC Team on 28nm Lithography Verification
Source: edageek.com
Date: 06-23-2009 21:15:16 GMTSynopsys and TSMC Deliver Accurate Lithography Verification for 28nm Designs
Source: www.nanowerk.com
Date: 06-23-2009 13:50:17 GMTSynopsys and TSMC Deliver Accurate Lithography Verification for 28nm Designs - Zibb.com
Source: Comtex
Date: 06-23-2009 09:00:00 GMTSynopsys And TSMC Deliver Accurate Lithography Verification For 28nm Designs
Source: www.semiconductoronline.com
Date: 06-23-2009 06:39:00 GMT
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I haven't heard of failure rates in products for other memories. What is a...
benchmarker– 5/19/2009 11:07:00 AM CDT
in response to Everspin MRAM Cited for Zero DefectsEverspin was spunoff from Freescale last summer and not several years ago. ...
Hal– 5/18/2009 2:20:00 PM CDT
in response to Everspin MRAM Cited for Zero DefectsTradeshows are no longer profitable or fun for those who have toattend...
Walt Rutenbar– 3/16/2009 11:24:00 AM CDT
in response to EUV Litho Needs Metrology SupportThe fact is that regardless all the hype, EUV lithography isn\'tgoing to...
LOOKCLOSER– 3/12/2009 10:39:00 AM CDT
in response to EUV Litho Needs Metrology Support
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Technical Articles
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Control Strategy for Wafer-Edge Defects
M.F. Hsu and J.H. Yang, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Hsinchu, Taiwan; E. Yang, H. Chen, M. Ng, M. Li and C. Perry-Sullivan, KLA-Tencor Corp., Milpitas, Calif. 06/01/09Identifying and resolving systematic process issues on edge die before they migrate to interior die prevents production yield loss and enables faster yield ramp. -
OEE Focuses a Slow Economy
Ruth DeJule, Contributing Editor 04/01/09With years of double-digit annual growth, fabs and equipment suppliers alike are learning to make the most of decreasing demands in a ramp-down environment, including the use of overall equipment efficiency (OEE). -
Controlling Process-Induced Charging Heightens Productivity
Ralph Spicer, Jeff Hawthorne, Darryl Peters and Robert Newcomb, Qcept Technologies, Atlanta 03/01/09Process-induced charge defects are becoming a yield issue for next-generation devices, prompting the need for enhanced control during wafer processing.
Events
BrightSpots 3D IC Forum
Dates: 07-24, 2009Location:2009 International Workshop on EUV Lithography
Dates: 07-17, 2009Location: Sheraton Waikiki, HonoluluTopical Workshop on Wire Bonding
Dates: 07-13, 2009Location: San Francisco, Calif.



