Yield Management

• IMEC, Synopsys to Co-Develop 3-D Stacked ICs

  Staff, March 9, 2010
  IMEC will use Synopsys TCAD tools in a collaboration to address reliability and performance concerns in through-silicon via (TSV) technology.  More

• AMD, Intel Vie on Power Savings Ideas

  David Lammers, News Editor, February 9, 2010
  At ISSCC, AMD and Intel engineers offer competing views on how to keep power consumption under control. AMD introduced its 32 nm SOI processor, Llano, and Intel discussed its 32 nm Westmere family. Intel Labs staff presented conference papers on how to conserve watts while dealing with manufacturing variability.  More

• Allvia Offers New TSV Reliability Data

  Sally Cole Johnson, January 25, 2010
  Allvia is stepping forward with details about its full reliability tests, and the data may help customers decide which products are feasible, said CEO Sergey Savastiouk. To avoid CTE issues, Allvia uses a silicon interposer between two stacked substrates and connects them with TSVs. "Our target is to add passive elements on the substrate," he said.  More

• AMD Constrained on 40 nm GPUs From TSMC

  David Lammers, News Editor, January 22, 2010
  AMD executives said the company is "heavily constrained" now on shipments of its 40 nm graphics processors, made at TSMC. "We are seeing progress both in the delivery of wafers and the underlying yields. But we are constrained today," AMD CEO Dirk Meyer said.  More

• Silicon Interposers Bridge to 3-D TSVs

  Philip Garrou, Contributing Editor - Microelectronic Consultants of NC, December 22, 2009
  The RTI 3-D-ASIP conference attracted most of the top players in the industry, who outlined the challenges still facing 3-D volume manufacturing, including wafer thinning yields and the need for better EDA tools. Many of the speakers said they see silicon interposers with TSVs (silicon 2.5-D) as a bridge to full 3-D ICs.  More

• Nvidia's Chen Calls for Zero Via Defects

  David Lammers, News Editor, December 7, 2009
  Nvidia needs zero defects from its foundry partners, particularly in the vias on its leading-edge graphics processors, said John Chen, vice president of technology and foundry operations at the GPU powerhouse. With 3.2 billion transistors on its 40 nm graphics processor now coming on the market, the 7.2 billion vias have become a source of problems that the industry must learn to deal with, Chen said in a keynote speech at IEDM.  More

• TCAD Enables Robust Process Development and Manufacturing

  Yoshiyuki Shioyama and Seiji Onoue, Toshiba Corp., Tokyo, January 8, 2010
  Toshiba has developed a TCAD-based methodology which reduces process development costs and time. The approach allows the process window to be optimized before transfer to manufacturing, contributing to faster yield improvements.  More

• Intel Chip Vision: Run Slow to Stay Cool

  David Lammers, News Editor, November 18, 2009
  Keeping power under control at data centers is causing a radical reassessment of chip design, according to Shekhar Borkar, Intel's director of MPU research. Cramming many cores on a die, most of them running at very low frequencies at operating voltages of less than half a volt, is likely to happen over the next decade. And self-aware systems will poll the processors about chip aging issues, such as NBTI.  More

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