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Yield Management

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The latest news and information on semiconductor yield management, including process control, reliability, defect detection and design for manufacturing.

  • CyberOptics Founder Steven Case Killed in Plane Crash

    Staff, June 17, 2009
    CyberOptics said its chairman and founder Steven Case died Tuesday night when the small plane he was flying crashed. Case founded the company, which makes yield improvement sensors, 25 years ago.  More
  • Komatsu Laser Marks on Silicon Surface

    Kenji Tsuda, Asia Contributing Editor, June 2, 2009
    Laser330 Komatsu Engineering Corp. said it has developed a laser marker that can better identify silicon-based ICs used in applications where chip identification is important, including automotive, medical and computer equipment. The laser irradiates a small portion of the chip, creating a concave surface that forms a 16×16 dot surface.  More
  • Control Strategy for Wafer-Edge Defects

    M.F. Hsu and J.H. Yang, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Hsinchu, Taiwan; E. Yang, H. Chen, M. Ng, M. Li and C. Perry-Sullivan, KLA-Tencor Corp., Milpitas, Calif., June 1, 2009
    Identifying and resolving systematic process issues on edge die before they migrate to interior die prevents production yield loss and enables faster yield ramp.  More
  • Everspin MRAM Cited for Zero Defects

    Staff, May 18, 2009
    Everspin Technologies, a venture-backed MRAM manufacturer that spun out of Freescale last year, said it has passed reliability tests at a key customer. Siemens said its touch-screen interface panels have seen zero defects after two years in ~100,000 units. The MRAMs provide nonvolatile storage, replacing battery-backed SRAMs.  More
  • Mentor Enhancing Yield Diagnostics Tool

    David Lammers, News Editor, May 6, 2009
    TestData330 Mentor Graphics is adding more powerful statistical analysis techniques to its yield diagnostics tool, Yield Assist. The technique can narrow down problem areas on the die, and shorten the time required for failure analysis.  More
  • IMEC Sends Memory DFM Tool to Samsung Electronics

    Staff, April 21, 2009
    IMEC has transferred its Memory Variability Aware Modeling tool to Samsung Electronics. The design-for-manufacturing (DFM) tool predicts yield loss of SRAMs caused by the process variations of deep-submicron IC technologies.  More
  • IDMs, Fabless Face Reliability Challenges

    David Lammers, News Editor, April 15, 2009
    IRPS330 Managers from Broadcom, Intel and Xilinx are among the invited speakers at the upcoming International Reliability Physics Symposium. The varying approaches to reliability by the large IDMs and the major fabless vendors that rely on foundries is a theme at this year’s IRPS, scheduled for April 26-30 in Montreal.  More
  • 3-D Equals Two Generations of Scaling

    Philip Garrou, Microelectronics Consultants of North Carolina, Research Triangle Park, N.C., April 2, 2009
    MIT330 North Carolina State Professor Paul Franzon said the need for 3-D ICs is becoming more acute as CMOS scaling improvements (according to MIT projections) halt at the 32 nm node and beyond. However, 3-D yield and design challenges remain, according to IBM and Cadence technologists who participated in a IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas.  More

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Technical Articles

  • Control Strategy for Wafer-Edge Defects

    M.F. Hsu and J.H. Yang, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Hsinchu, Taiwan; E. Yang, H. Chen, M. Ng, M. Li and C. Perry-Sullivan, KLA-Tencor Corp., Milpitas, Calif. 06/01/09
    Identifying and resolving systematic process issues on edge die before they migrate to interior die prevents production yield loss and enables faster yield ramp.
  • OEE Focuses a Slow Economy

    Ruth DeJule, Contributing Editor 04/01/09
    With years of double-digit annual growth, fabs and equipment suppliers alike are learning to make the most of decreasing demands in a ramp-down environment, including the use of overall equipment efficiency (OEE).
  • Controlling Process-Induced Charging Heightens Productivity

    Ralph Spicer, Jeff Hawthorne, Darryl Peters and Robert Newcomb, Qcept Technologies, Atlanta 03/01/09
    Process-induced charge defects are becoming a yield issue for next-generation devices, prompting the need for enhanced control during wafer processing.

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