• What's New at SEMICON West 2009?

  SEMI, San Jose, June 5, 2009
  The most prominent new addition to the SEMICON West show this year is Extreme Electronics, a "show-within-the-show" spotlighting printed and flexible electronics, MEMS, solid-state lighting and nanoelectronics. However, the core of the show remains rooted in the challenges of Moore's Law and semiconductor manufacturing.  More

• Sematech Crafts ZIL Solution for 16 nm

  David Lammers, News Editor, June 29, 2009
  Sematech researchers said a zero interface layer (ZIL) approach has been demonstrated, and may be brought into chip manufacturing within the next few years. By eliminating the oxide interface layer between the high-k dielectric and the silicon channel, the EOT can be sharply improved, reducing short channel effects while improving the drive current.  More

• SEMICON West Session Focuses on 22 nm Lithography

  SEMI, San Jose, June 25, 2009
  Moderated by Semiconductor International Executive Editor Aaron Hand, the "Lithography Challenges and Solutions" session at the Device Scaling TechXPOT at SEMICON West (located in North Hall at Moscone Center) will feature technologists from across the semiconductor supply chain.  More

• Thin SOI Devices Shine at VLSI Symposium

  David Lammers, News Editor, June 18, 2009
  At the 2009 Symposium on VLSI Technology in Kyoto, Japan, an IBM R&D team described fully depleted CMOS devices created on extremely thin silicon-on-insulator (ETSOI) wafers, aimed at the 22 nm node and beyond. A Hitachi team presented SRAMs fabbed on ultrathin buried oxide SOI. Both avoided ion implantation steps.  More

• NEC's MRAM Uses Vertical Magnetic Spin

  Kenji Tsuda, Asia Contributing Editor, June 17, 2009
  NEC presented a spintronics MRAM cell at the Symposium on VLSI Technology in Kyoto, Japan. The cell uses a vertical magnetic structure that may be scalable to sizes smaller than today's SRAM cells, NEC said.  More

• Alliance Members Tout Oxide EOT Advance

  David Lammers, News Editor, June 16, 2009
  Researchers from GlobalFoundries and IBM Research went to the 2009 Symposium on VLSI Technology in Kyoto, Japan, to report progress in reducing the effective oxide thickness (EOT) in the gate stacks for both nFET and pFET devices. The team says it has exceeded EOT and other performance targets set for the 22 nm node.  More

• IMEC Tips 10 nm Options at Tech Forum

  Laura Peters, Editor in Chief, June 11, 2009
  IMEC Fellow Marc Heyns described R&D directions at the consortium's recent technology forum, including 10 nm devices with high-mobility channels based on germanium and III-V materials. Heyns said that recent studies at IMEC revealed that germanium oxide (GeO₂), when grown under the right conditions on silicon, is actually a better insulator than the SiO₂.  More

• EUV Reduced to an Engineering Problem

  Laura Peters, Editor-in-Chief, June 9, 2009
  EUV seems to be finally at the stage of "just an engineering problem," though a sufficiently powerful and reliable source has yet to be worked out. ASML's Martin van den Brink said his company plans to introduce a production EUV tool, capable of delivering 60 wph throughput, next year.  More

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