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The latest information on semiconductor packaging including wafer-level and chip-scale 3-D integration, wafer bumping, die and wire bonding, and encapsulation.

  • Cost a Major Challenge for Advanced Packaging Solutions

    Jan Vardaman, President, TechSearch International, Austin, Texas, July 2, 2009
    Semiconductor Packaging Over the past several years, IDMs have seen the price of silicon fabrication fall, while the cost of packaging, assembly and test has steadily been on the rise.  More
  • New Packaging Dimensions, Frontiers

    SEMI, San Jose, July 2, 2009
    Packaging technologies are very much at the fore of industry thinking, driven by ICs at 22 nm design rules, 3-D designs, MEMS devices and biomedical applications. Advanced packaging technologies are part of the technology showcase at SEMICON West 2009.  More
  • Wafer-Level Packaging in Africa?

    Sally Cole Johnson, Contributing Editor, July 1, 2009
    Nemotek Technologie Yes, Africa. Nemotek Technologie is manufacturing wafer-level optics and packaging in its state-of-the-art facility located in Morocco's Rabat Technopolis Park.  More
  • SUSS MicroTec, 3M Partner on 3-D Bonds

    Phillip Garrou, Consultant, Microelectronics Consultants of North Carolina, Research Triangle Park, N.C., June 22, 2009
    SUSS Temporary Bonding SUSS MicroTec AG (Garching, Germany) and 3M Corp. (Minneapolis) will work together, offering 3M's temporary bonding process as part of the new SUSS 300 mm bonder line.  More
  • Emerging Trends in Advanced Packaging

    Mahadevan Iyer, Texas Instruments, Dallas, June 1, 2009
    As electronic products find applications in personal, healthcare, home, automotive, environmental and security systems and become ubiquitous in everyday life, new packaging technologies and materials will be required.  More
  • Wafer-Level Packages Set Sights on Large Die

    Guilian Gao and Kenneth Honer, Tessera, San Jose, June 1, 2009
    Wafer-level package (WLP) technology is steadily proliferating into an increasing number of small-die applications. Volume production has proven elusive for large-die applications such as DRAM and flash memory, but an ideal WLP — reliable and capable of high-frequency operation — could change this situation.  More
  • Downturn to Spur Shift to 3-D Packaging

    Sally Cole Johnson, Contributing Editor, May 27, 2009
    Package330 The past several semiconductor downturns have resulted in transitions from one generation of packaging to the next. This one’s no exception. “Out of this downturn, we’re rapidly shifting from 2-D to 3-D packaging,” said Jim Walker, vice president of semiconductor manufacturing research at Gartner Inc.  More
  • Infrastructure Still Inhibits 3-D ICs

    Ruth DeJule, Contributing Editor, May 20, 2009
    Ruth330 The industry is challenged to identify the most cost-effective stacking, bonding and integration methods.  More

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Sandisk Uses Nine-Chip Stack in Latest microSD Card
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June 10, 2009
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June 06, 2009
Experience or Prejudice? The Case for Silicon Interposers
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Technical Articles

  • Emerging Trends in Advanced Packaging

    Mahadevan Iyer, Texas Instruments, Dallas 06/01/09
    As electronic products find applications in personal, healthcare, home, automotive, environmental and security systems and become ubiquitous in everyday life, new packaging technologies and materials will be required.
  • Infrastructure Still Inhibits 3-D ICs

    Ruth DeJule, Contributing Editor 05/20/09
    The industry is challenged to identify the most cost-effective stacking, bonding and integration methods.
  • Flip-Chip Packaging Becomes Competitive

    Sally Cole Johnson, Contributing Editor 05/19/09
    The cost and performance benefits of flip-chip packaging, combined with the increased cost of gold bonding wire, have made flip-chip technology competitive for applications ranging from cell phones to gaming chips.

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