Semiconductor Packaging

• Fan-Out Packaging Dispute Resolves in IP Licensing Deal

  Sally Cole Johnson, Contributing Editor, February 3, 2010
  What began as a patent dispute over fan-out packaging technologies has resulted in an IP agreement that will ultimately make it easier for packaging subcontractors to license Epic's ChipsFirst and Freescale's RCP technologies in one step, said James Kohl, Epic's CEO.  More

• TI Boosts Spending on Assembly and RFAB

  David Lammers, News Editor, January 27, 2010
  With demand strong for computer power ICs, LED TV backlight controllers and other analog products, Texas Instruments is expanding test and assembly capacity to meet customer delivery agreements. Also, a pilot line at the new 300 mm analog RFAB is up and running, and TI expects full production there by the end of the year.  More

• Allvia Offers New TSV Reliability Data

  Sally Cole Johnson, January 25, 2010
  Allvia is stepping forward with details about its full reliability tests, and the data may help customers decide which products are feasible, said CEO Sergey Savastiouk. To avoid CTE issues, Allvia uses a silicon interposer between two stacked substrates and connects them with TSVs. "Our target is to add passive elements on the substrate," he said.  More

• GlobalFoundries Adds Qualcomm, Supports Gate-First Technology at 28 nm Generation

  David Lammers, News Editor, January 7, 2010
  GlobalFoundries is adding Qualcomm to its customer base, starting with 45 nm wafers and moving to a 28 nm LP process that includes high-k/metal gate technology. Prior to the announcement, John Pellerin, director of technology development at GlobalFoundries, said the gate-first approach to high-k deposition has die size advantages over the gate-last approach supported by rival foundry TSMC.  More

• Binghamton U. Offers R&D Collaboration

  Sally Cole Johnson, Contributing Editor, December 28, 2009
  Binghamton University's New York State Center of Excellence in Small Scale Systems Integration & Packaging (S³IP) works on a wide variety of R&D projects with industry, and makes its state-of-the-art facilities and tools available to partners and members. R&D collaboration with universities is becoming an appealing option for many companies looking to share costs, center officials said.  More

• Despite Downturn, 3-D Spending Continues

  Philip Garrou, Contributing Editor - Microelectronic Consultants of NC, December 23, 2009
  Investments in 3-D integration continue, analysts said at the the RTI 3-D Architectures for Semiconductor Integration and Packaging conference. Analyst Jan Vardaman at TechSearch said she is tracking more than 50 3-D IC programs worldwide. Yole Developpement has identified 15 300 mm 3-D TSV pilot lines.  More

• Silicon Interposers Bridge to 3-D TSVs

  Philip Garrou, Contributing Editor - Microelectronic Consultants of NC, December 22, 2009
  The RTI 3-D-ASIP conference attracted most of the top players in the industry, who outlined the challenges still facing 3-D volume manufacturing, including wafer thinning yields and the need for better EDA tools. Many of the speakers said they see silicon interposers with TSVs (silicon 2.5-D) as a bridge to full 3-D ICs.  More

• Nvidia's Chen Calls for Zero Via Defects

  David Lammers, News Editor, December 7, 2009
  Nvidia needs zero defects from its foundry partners, particularly in the vias on its leading-edge graphics processors, said John Chen, vice president of technology and foundry operations at the GPU powerhouse. With 3.2 billion transistors on its 40 nm graphics processor now coming on the market, the 7.2 billion vias have become a source of problems that the industry must learn to deal with, Chen said in a keynote speech at IEDM.  More

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