Materials

• Group Opposing 450 mm N.Y. Subsidy

  David Lammers, News Editor, February 8, 2010
  A "Concerned Citizen Group" is opposing any New York State funding for a 450 mm wafer development center at CNSE/Sematech in Albany, N.Y. The group told New York politicians that any state funding for 450 mm development would not benefit companies operating in the state, and would be a "reckless waste of taxpayer money."  More

• Crystal Growth Points to Defect-Free Thin Films

  Alexander E. Braun, Senior Editor, February 1, 2010
  Cornell University researchers said colloidal research may lead to the discovery of principles that will enable the growth of defect-free thin films. The team led by Professor Itai Cohen tested conditions that lead to smooth crystal growth, and discovered that the random darting motion of the particles is a key factor affecting how crystals grow.  More

• Nanotech Moves on Toward Better Times

  Alexander E. Braun, Senior Editor, January 21, 2010
  Nanotech is feeling the economic downturn, and much of the venture capital for most nano enterprises has dried up. Nevertheless, there is optimism for a strong recovery by 2015. Mark Bünger, director of research at Lux Research Inc. (Boston), said the current economic environment has caused his firm to reassess its predictions. "These changes will put large corporations in the driver's seat, force startups to break even or bust, and demand creative action from governments."  More

• GlobalFoundries Adds Qualcomm, Supports Gate-First Technology at 28 nm Generation

  David Lammers, News Editor, January 7, 2010
  GlobalFoundries is adding Qualcomm to its customer base, starting with 45 nm wafers and moving to a 28 nm LP process that includes high-k/metal gate technology. Prior to the announcement, John Pellerin, director of technology development at GlobalFoundries, said the gate-first approach to high-k deposition has die size advantages over the gate-last approach supported by rival foundry TSMC.  More

• CMOS Transitions to 22 and 15 nm

  David Lammers, News Editor, January 1, 2010
  Scaling beyond the 22 nm node is likely to require fully depleted CMOS, either on SOI or bulk wafers. TSV 3-D interconnects and SiC stressors also appear likely to be implemented, while the jury is still out on when vertical finFETs and III-V devices will be widely implemented.  More

• NEC Ups Frequency With PTL Interconnects

  David Lammers, News Editor, December 30, 2009
  NEC Electronics has developed techniques that create thicker copper contacts for analog and RF transistors implemented on wireless SoCs in a low-power 40 nm technology. The partially thickened local (PTL) contacts cut the resistance and improve the RF F_max to ~200 GHz for a 40 nm technology. The technique could prove useful for single-chip solutions aimed at next-generation wireless standards.  More

• MIRAI Advances Ge Transistor Prototype

  Kenji Tsuda, Asia Contributing Editor, December 29, 2009
  Japan's MIRAI consortium said it has created a germanium p-type transistor prototype with a LaAlO₃ high-k dielectric, part of a plan to develop a germanium-based CMOS technology at the 2X technology node and beyond.  More

• IBM Gains Confidence in 22 nm ETSOI

  David Lammers, News Editor, December 15, 2009
  At the IEDM conference in Baltimore, IBM researchers indicated that a fully depleted CMOS on extremely thin SOI wafers may be the way to go at the 22 nm node. The approach allows reduced short channel effects, and supports gate length scaling to 25 nm and beyond. The fully depleted technology involves Soitec, which supplies wafers with a thin silicon layer on top of the buried oxide.  More

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