• Sematech Crafts ZIL Solution for 16 nm

  David Lammers, News Editor, June 29, 2009
  Sematech researchers said a zero interface layer (ZIL) approach has been demonstrated, and may be brought into chip manufacturing within the next few years. By eliminating the oxide interface layer between the high-k dielectric and the silicon channel, the EOT can be sharply improved, reducing short channel effects while improving the drive current.  More

• Printable Electronics Hits Display Needs

  Michael P.C. Watts, Impattern Solutions, Austin, Texas, June 24, 2009
  Printable electronics could reduce the cost of making flexible displays of the kind used in the Kindle and other E-books. At the recent SID 2009 conference, researchers discussed the marriage of printable electronics and low-power displays used in emerging portable devices, which must be light, flexible, low-power, and readable in ambient light.  More

• SUSS MicroTec, 3M Partner on 3-D Bonds

  Phillip Garrou, Consultant, Microelectronics Consultants of North Carolina, Research Triangle Park, N.C., June 22, 2009
  SUSS MicroTec AG (Garching, Germany) and 3M Corp. (Minneapolis) will work together, offering 3M's temporary bonding process as part of the new SUSS 300 mm bonder line.  More

• Nanoelectronics Edge Into Production

  Paula Doe, Contributing Editor, SEMI, San Jose, June 19, 2009
  Graphene and spin wave transistors are among the technologies that look interesting for next-generation FETs. Near term, nanoelectronics products are entering commercial production. At SEMICON West, nanoelectronics challenges are part of the show's Extreme Electronics series on emerging technologies.  More

• Printed Electronics Seeing Wide Progress

  Paula Doe, Contributing Editor, SEMI, San Jose, June 19, 2009
  Executives from an array of printed electronics companies will describe progress in the field at SEMICON West. Materials, equipment and manufacturing processes for printed electronics are a focus at the show, including a July 16 session on Manufacturing Technology for Commercial Printed and Flexible Electronics.  More

• Thin SOI Devices Shine at VLSI Symposium

  David Lammers, News Editor, June 18, 2009
  At the 2009 Symposium on VLSI Technology in Kyoto, Japan, an IBM R&D team described fully depleted CMOS devices created on extremely thin silicon-on-insulator (ETSOI) wafers, aimed at the 22 nm node and beyond. A Hitachi team presented SRAMs fabbed on ultrathin buried oxide SOI. Both avoided ion implantation steps.  More

• NEC's MRAM Uses Vertical Magnetic Spin

  Kenji Tsuda, Asia Contributing Editor, June 17, 2009
  NEC presented a spintronics MRAM cell at the Symposium on VLSI Technology in Kyoto, Japan. The cell uses a vertical magnetic structure that may be scalable to sizes smaller than today's SRAM cells, NEC said.  More

• Alliance Members Tout Oxide EOT Advance

  David Lammers, News Editor, June 16, 2009
  Researchers from GlobalFoundries and IBM Research went to the 2009 Symposium on VLSI Technology in Kyoto, Japan, to report progress in reducing the effective oxide thickness (EOT) in the gate stacks for both nFET and pFET devices. The team says it has exceeded EOT and other performance targets set for the 22 nm node.  More

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