Materials

CMOS Transitions to 22 and 15 nm
David Lammers, News Editor, January 1, 2010
Scaling beyond the 22 nm node is likely to require fully depleted CMOS, either on SOI or bulk wafers. TSV 3-D interconnects and SiC stressors also appear likely to be implemented, while the jury is still out on when vertical finFETs and III-V devices will be widely implemented. More
NEC Ups Frequency With PTL Interconnects
David Lammers, News Editor, December 30, 2009
NEC Electronics has developed techniques that create thicker copper contacts for analog and RF transistors implemented on wireless SoCs in a low-power 40 nm technology. The partially thickened local (PTL) contacts cut the resistance and improve the RF F_max to ~200 GHz for a 40 nm technology. The technique could prove useful for single-chip solutions aimed at next-generation wireless standards. More
MIRAI Advances Ge Transistor Prototype
Kenji Tsuda, Asia Contributing Editor, December 29, 2009
Japan's MIRAI consortium said it has created a germanium p-type transistor prototype with a LaAlO₃ high-k dielectric, part of a plan to develop a germanium-based CMOS technology at the 2X technology node and beyond. More
IBM Gains Confidence in 22 nm ETSOI
David Lammers, News Editor, December 15, 2009
At the IEDM conference in Baltimore, IBM researchers indicated that a fully depleted CMOS on extremely thin SOI wafers may be the way to go at the 22 nm node. The approach allows reduced short channel effects, and supports gate length scaling to 25 nm and beyond. The fully depleted technology involves Soitec, which supplies wafers with a thin silicon layer on top of the buried oxide. More
UMC Takes Hybrid Approach to 28 nm High-k
David Lammers, News Editor, December 14, 2009
At IEDM, foundry UMC described a hybrid approach to high-k/metal gate deposition that seeks to take advantage of both the gate-first and gate-last approaches for 28 nm transistors. The hybrid scheme compares with a gate-last method supported by rival Taiwan foundry TSMC, and a gate-first approach by GlobalFoundries for the 28 nm generation. More
Intel Takes 32 nm PMOS to Record Levels
David Lammers, News Editor, December 10, 2009
At IEDM, Intel manager Paul Packan said Intel's flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device. "For the first time, linear drive currents on the PMOS have overtaken NMOS," he said. The sharp gain in PMOS performance comes partly by adding germanium to the SiGe stressors, and from the replacement-gate process. More
Pressure Builds on Gate First High-k
David Lammers, News Editor, December 9, 2009
Problems with the gate-first approach to high-k/metal gate deposition may force IBM to switch to the gate-last approach pioneered by Intel, technologists said this week at the International Electron Devices Meeting (IEDM) in Baltimore. GlobalFoundries and other members of the Fishkill Alliance are putting pressure on IBM to reconsider its gate-first approach, which technologists said has problems with yields, threshold voltage stability, and mobilities. More
Silicon May Prevail Despite Power Fears
David Lammers, News Editor, December 7, 2009
Speakers at an IEDM short course on scaling challenges said planar devices made in bulk silicon CMOS are likely to continue to be the basic technology platform for the next decade, despite concerns about power consumption. While III-V and germanium channels offer high mobilities and lower operating voltages, the challenges of cost, manufacturing complexity, and finding a workable gate dielectric may prevent adoption. Scott Thompson, organizer of the short course, said one exception may be Intel, which he said is seriously considering a tri-gate transistor for the outer nodes. More
Researchers Strive for Copper TSV Reliability
Philip Garrou, Contributing Editor, December 3, 2009
Moving 3-D TSVs to high-volume manufacturing will require rock-stable TSV reliability. Although copper CTE-related issues have appeared during recent scale-up activities, IMEC and other research centers are beginning to come up with solutions. More
Applied Introduces Dual-Wafer CMP System
David Lammers, News Editor, November 30, 2009
Applied Materials introduced the Reflexion GT system at Semicon Japan. The CMP tool polishes two 300 mm wafers at the same time, using two polishing heads on a pad that is 1.5× larger than today's single-wafer CMP pads. The tool has shipped to several logic and memory vendors. The leading pad vendors are offering 42 in. diameter pads. More
Rugged Nano Films to Enable Applications
Alexander E. Braun, Senior Editor, November 16, 2009
Stronger nanoparticle films that are easier to handle have been developed by Vanderbilt University researchers. "Our films are so resilient that we can pick them up with a pair of tweezers and move them around on a surface without tearing," said James Dickerson, assistant professor of physics at Vanderbilt. More
Nikko Metals Offers Hybrid 450 mm Wafers
David Lammers, News Editor, November 6, 2009

Nikko Metals, a subsidiary of Nippon Mining and Metals, is readying hybrid 450 mm wafers that sinter a 300 mm single-crystal silicon wafer inside a 450 mm polycrystalline wafer. The goal is to save money for companies developing process equipment targeted to the 450 mm wafer diameter.
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Sematech 3-D Program Provides Lessons
David Lammers, News Editor, November 2, 2009
Sematech's 3-D interconnect program has provided the equipment and materials industry with a proving ground over the last 18 months. Andy Rudack, a Sematech metrology engineer, noted that the bonded wafers exceed the SEMI standard for wafer thickness and weight, presenting a variety of readily solvable challenges. More
New Multiferroic Materials Promise Exotic Devices, Faster Computing
Alexander E. Braun, Senior Editor, October 29, 2009
A multidisciplinary collaboration has led to the creation of a new multiferroic material with great potential for next-generation electronics. The theory started with Argonne Lab's Craig Fennie's principles of microscopic materials design, and could potentially end with new device structures that can independently write electrically and read magnetically. More
SOI Reduces Dynamic Power, Wafer Costs Coming Down
David Lammers, News Editor, October 12, 2009
Silicon-on-insulator (SOI) technology is seeking to penetrate the high-volume market for mobile Internet devices and smart phones. An ARM paper at last week's IEEE International SOI Conference compared power consumption levels for bulk and SOI. And wafer supplier Soitec said it anticipates volume wafer prices in the $500 range. More
Leti Claims Silicon Nanowire Integration Breakthrough
Staff, October 7, 2009
Leti researchers have claimed progress in integrating silicon nanowires with CMOS, at temperatures compatible with CMOS processes. By oxidizing the catalyst for copper nanowires, the Leti team contravened conventional wisdom about oxygen's impact on nanowire growth. More
IBM Readies 32 nm eDRAM With Low Latency
David Lammers, News Editor, September 18, 2009
IBM unveiled a 32 nm SOI embedded DRAM, and will provide details at the upcoming IEDM in December. Gary Patton, vice president for IBM's SRDC, said the SOI eDRAM has latency and cycle times of <2 ns, uses 4× less standby power, and has "up to a 1000× lower soft-error rate (SER), better power savings, and reliability comparable to a similar SRAM." More
Samsung Upgrading Austin NAND Fab
David Lammers, News Editor, August 14, 2009
Samsung said it will convert an older 200 mm DRAM fab in Austin into a copper BEOL for the adjacent 300 mm NAND fab. The upgraded Austin fab will ready for 3X NAND production as early as late 2010. More
Midwest MicroDevices Expands MEMS Capabilities
David Lammers, News Editor, August 4, 2009
Midwest MicroDevices said it has expanded its technical capabilities. The foundry, which specializes in thin-film fabrication, now can handle MEMS production on flexible substrates, and can evaporate exotic materials without breaking vacuum. It also developed a prototype TSV capability. More
GlobalFoundries Outlines 22 nm Roadmap
David Lammers, News Editor, July 28, 2009
GlobalFoundries plans to introduce embedded silicon carbon (eSiC) to strain the nFET transistors at the 22 nm node, said John Pellerin, director of technology development. Through-silicon vias also are on the roadmap, but air gaps are not, Pellerin said prior to the groundbreaking ceremony of Fab 2 in Malta, N.Y. More