Perspectives From the Leading Edge

May 2, 2008 | Link This | Email this | Comments (0)

At the recent TSMC “open innovation platform” meeting they described among other things their plans to “…collaborate in the early stages of the IC design process” with their customers. My personal interest lies more in the details they disclosed about their plans for post back end of line activity. According to TSMC's new roadmap, the company is putting more resources into two areas: stacked die packages and 3D.

This announcement should be of concern to the contract assembly and test houses (Amkor, ASE, SPIL, STATS ChipPAC, etc. since such an expansion of services by TSMC will mean a potential loss of business for these assembly houses. While it is unlikely TSMC will produce stacked packages, TSMC has already developed 65-nm wirebond and flip-c...Read More

April 19, 2008 | Link This | Email this | Comments (0)

By now, if you’re a reader of this blog, you know that I am preaching that 3D IC intregration will happen in an evolutionary not revolutionary fashion (which is how all things have happened in microelectronics over the past 50 years.

We have mentioned several times that 3D process flows have three unit operations in common: (a) TSV formation; (b) thinning and (3) bonding. Since thinning has been optimized in numerous other applications, the infrastructure is currently focused on introducing TSVs and bonding into mainstream production. Bonding technology without TSVs has been introduced by Infineon and Sony and TSVs without bonding are being commercialized by the various image sensor fabricators that we have been discus...Read More

April 13, 2008 | Link This | Email this | Comments (0)

Finishing up on my coverage of the 3D Integration technology from last months IMAPS Device Packaging Conference in AZ........

NXP Passive Integration Devices to contain TSV

Yannou from NXP (the Philips semiconductor spinout) gave a very nice presentation on their integrated passive technology which they call PICS (passive integration and connecting substrate). We are not talking about Imbedded passives which are passives buried in PWB layers, but rather thin film components similar to what ST Micro has been manufacturing for several years (and they call IPADs).

Their cap...Read More

March 30, 2008 | Link This | Email this | Comments (0)

This week I’m continuing to share information from the recent IMAPS Device Pkging meeting that was held on the Ft. McDowell reservation north of Scottsdale AZ. Must be because of the time I grew up....but as I type Ft McDowell my mind begins to wander to those great late 1950s westerns .... MGM proudly presents ”Ft McDowell” starring John Wayne, Gabby Hayes and Rita Haywerth. Anyway back to technology......

IMEC

Before I get to presentations and rumors from the meeting I’d like to share with you a new process variation that has been developed by Eric Beyne and the other 3D researchers at IMEC. As you can see from the figure below they first bond th...Read More

March 23, 2008 | Link This | Email this | Comments (0)

The casino was second rate, the food in the casino was third rate but the information on 3D IC integration was priceless. The IMAPS Device Packaging Conference, attended by well over 500 professionals, is now history. In the next few blogs I will go over some of the significant information gleaned from the presentations and the side conversations in the hall ways.

First lets start with CIS (CMOS Image Sensor) packaging. If you’ve been keeping up with these blogs you know that Toshiba, Oki-Zycube and most recently ST Micro have announced 2008 production capacity for this wafer level packaging technology which uses backside TSV. In my last blog I pointed out that ST Micro is a...Read More