Peering into Nanocrystal NAND

Freescale Semiconductor’s
assertion that nanocrystal (NC) NOR flash will go into
manufacturing next year raises the question: Can nanocrystals
be employed to extend NAND flash scaling?

NAND is a much bigger market than
NOR now, and its potential is nearly as limitless as the data we
store. However, NAND faces the same scaling and reliability
challenges that NOR faces. As the polysilicon floating gate becomes
smaller, fewer electrons are used to store a single bit. Any
rupture in the floating gate allows the electrons to leak away,
presenting reliability challenges.

The problem has spurred research
into phase-change memories (PCMs), which have great potential but
face heat-related issues, according to one memory analyst who
declined to be quoted by name. PCMs use electrodes to deliver heat
to a small section of chalcogenide material, changing it from
amorphous to crystalline. At high temperature operation, the heat
in the chip’s operating environment can flip some bits, the
analyst said. (Many of the reader comments on the recent Chipworks
blog on the Numonyx PCM raise this point.)

Asked about
the possibility of adapting Freescale’s NC deposition
techniques to NAND flash, Freescale flash technology program
manager Gowrishankar Chindalore said, “In general, if you put
this into a NAND technology, the stack combination would be
different.” NAND flash uses Fowler-Nordheim tunneling, rather
than the hot electron injection method employed in NOR flash. To
create a NC NAND flash device, electrons would be injected from the
bottom to write, and pushed out from the bottom to erase.
“You would have to re-optimize the dielectrics around it and
change the dielectric thicknesses,” Chindalore said.

Interest in NC NAND
is widespread. The biggest NAND manufacturers, Toshiba Corp. and
Samsung Electronics, have published several papers on NC NAND
technology. Also, IBM Research has some great
images on its Web site from an IEDM presentation,  showing
self-assembling co-polymers which arrange nanocrystals into neat
rows and columns. And Professor Sanjay Banerjee at
the University of Texas at Austin has co-authored studies of
self-assembling nanocrystals, including SiGe NCs.

Flash analyst Jim Handy of Objective
Research said both NOR and NAND face similar reliability challenges
as scaling proceeds and the number of electrons in the floating
gate becomes smaller. Since NOR is used to store data, the
reliability issue is more important, which is why Freescale is
making the switch first. Handy said many flash vendors are
considering or now are using nitride charge trapping technology,
but NC technology could replace nitride charge trapping.
“Both nitride charge trapping and nanocrystals do the same
thing, storing the charge,” Handy said. However, because the
NCs act as separate islands of charge, they may demonstrate better
reliability after the 32 nm node, he added.

NC Scalability, the Numbers
Game

As scaling
proceeds, however, the number of NCs in each bit would decrease.
Chindalore said each NC is 10-15 nm in size. While the 90 nm
technology uses ~100 NCs to store a bit, the number would roughly
halve at each node, going to ~50 NCs at 65 nm, ~25 at 45 nm, ~12 at
32 nm, and so on. But that takes a static view of NC technology,
and someone may figure out how to make them smaller. In the
Freescale paper presented at the International Memory Workshop 2009
held in Monterey, Calif., the Freescale team discussed their
success at creating an enhanced coverage area process (ECP),
increasing the area covered by NCs from 30% to 60%.

Toshiba Has Double-Layer
SONOS Structure

Looking
ahead, Samsung researchers at IEDM have discussed FinFET-type NC
flash developments, studying the multi-level-cell (MLC)
capabilities. And CEA/Leti has presented some interesting work on
NC flash. At the 2008 IEDM, Toshiba engineers adapted a
silicon oxide nitride oxide semiconductor (SONOS) structure,
which retains electrons in a nitride layer formed inside the gate
insulator. The double tunneling layer structure sandwiches an
ultra-thin, 1.1 nm silicon nanocrystal layer between 1 nm thick
oxide films.

Research is wonderful. But Freescale
has put its money down on the table, taking the important step of
committing to NC technology for the high-reliability NOR flash
embedded on its microcontrollers. If making NCs is as
cost-effective as Chindalore says it is by using Freescale’s
proprietary deposition technology, it is safe to assume that NAND
memory powerhouses such as Samsung and Toshiba will either figure
out their own deposition techniques, or license from Freescale.