IEDM and the Intel Replacement Gate Update

Already, rumors are swirling at the
2008 International Electron Device Meeting, which kicked off Sunday
with two short courses here in cold and rainy San Francisco. A
high-k expert said he has heard that Intel Corp. may shift its
high-k/metal gate process for the 32 nm node, using a gate-first
flow for the nFET and the replacement metal gate (RMG) approach for
the pFET.

Maintaining the work function of the
pFET gate electrode metal is the more difficult challenge,
requiring the RMG approach. The replacement gate approach involves
depositing the hafnium-based gate dielectric and putting in a
polysilicon dummy gate which is stripped out and replaced after the
high-temperature processing steps are completed. By Monday
afternoon, Intel Senior Fellow Mark Bohr had scotched those
rumors, said the RMG approach is “proving scalable to 32
nm.” Bohr said RMG will be used for both the n and pFETs.
IEDM includes a Wednesday late paper to be presented by the
Intel 32 nm program manager Sanjay Natarajan.

Dick James, chief blogger at
Chipworks (Ottowa), said that last month Chipworks bought from a
distributor one of the 45 nm Opterons from Advanced Micro Devices
Inc. (Sunnyvale, Calif.). Intel has roughly a one-year lead on
AMD when it comes to 45 nm silicon.

Bohr said that Intel will reach a
milestone by the end of this year, shipping 100 million 45 nm MPUs
by year-end. He claimed that high-k/metal gate has not worsened
yields, and said the 45 nm production yields are the highest in
Intel’s history, surpassing its 65 nm yields.

Bohr noted that Intel is the only
company shipping a high-k/metal gate part, a move that AMD and IBM
will undertake at the 32 nm generation and TSMC at the 28 nm node.
With Intel saying that its 32 nm process will be ready for volume
manufacturing by the fourth quarter of 2009, it will be interesting
to see if IBM and its partners can close the gap somewhat, shipping
a 32 nm MPU with high-k/metal on a silicon-on-insulator (SOI)
technology by mid 2010. 

Intel continues
to emphasize its high drive current, while the Fishkill
alliance members say drive current is only one metric. With an SOI
technology the IBM gate capacitance is lower than Intel’s
bulk transistor, making the ring oscillator speed the best metric
to focus on. Without a paper from IBM and its SOI process partners
(AMD and Freescale Semiconductor Inc.) on its 32 nm SOI transistor,
this IEDM won’t see a direct showdown between Intel’s
best 32 nm transistor and the IBM device that will be directed at
the company’s servers.

The equipment industry and most of
the semiconductor manufacturers are focused on getting 32 nm
technology ready for production in the next couple of years. That
said, it may be the 22 nm generation that presents some
revolutionary changes. Kaizad Mistry, Intel’s 22 nm program
manager, agreed with an assertion that with EUV lithography not
ready, and with Kelin Kuhn of
Intel reporting that vertical multi-gate transistors are not
ready for prime time at 22 nm, Intel will have to turn other
knobs to enable the 22 nm node.

One question is
whether the (110) orientation wafers will provide a boost at the 22
nm node. Mistry wouldn’t comment, but he pointed to a paper
from Intel’s Paul Packan et al at IEDM later today on
Intel’s (110) orientation work. The paper, entitled High
Performance Hi-K + Metal Gate Strain Enhanced Transistors on (110)
Silicon, contends that (110) wafers deliver a 15% drive current
improvement for a 35 nm gate length CMOS.  Indeed, that Monday
session has two other papers on (110) orientation R&D, from
Fujitsu Ltd. and the University of Tokyo. And other (110)
orientation papers come during Session 23, from Toshiba and the
Tokyo Institute of Technology.

Apparently, (110) oriented lattices
have always provided a boost to the pFET, and they were used early
in the history of the chip industry. But for relatively large
devices with oxide dielectrics, the nFET degradation stemmed from
interface defects at the gate oxide. With the switch to high-k, the
defect densities don’t worsen on (110) wafers. The pFET
speeds up, the nFET suffers no degradation. And the costs are
roughly the same, as wafer manufacturers can make either (110) or
(100) wafers with equal dexterity. Rusty Harris, a former AMD
assignee to Sematech who now teaches at Texas A&M University,
led a Sematech (110) R&D effort at in 2007 that showed
significant pFET gains, at no additional process complexity. With
high-k on board, (110) could bail CMOS out, much as strained
silicon and immersion lithography have done.

Another spate of papers at this 2008
IEDM focus on adding Lanthanum to the hafnium-based high-k oxides.
A thin La layer reduces the oxide interface layer, improving the
k-value, but at the risk of higher defect densities.