RCP and the Front-End / Back-End Convergence

Freescale Semiconductor Inc.’s
Redistributed
Chip Packaging (RCP) technology is an effort that cries out for
standards and partners, and Freescale is working the issue.

Navjot Chhabra, RCP operations
manager at Freescale, was asked if Freescale’s RCP and
the
embedded wafer level ball grid array (eWLB) technology from
Infineon Technologies AG were both attempting to take advantage of
the same opportunities. Freescale and Infineon, Chhabra
said, “Have agreed to talk about a common roadmap for
this technology. They (Infineon) have a certain space. We are in
discussions so we don’t have a competing platform.”

Evidence of further cooperation
comes from the program
of next week’s Electronics Components and Technology
Conference (ECTC), planned for May 27-30 in Orlando. Several
Infineon engineers, and B. Dehlink of Freescale Halbleiter GmbH,
will jointly present a paper entitled “77 GHz SiGe Mixer in an
Embedded Wafer Level BGA Package.”

Last November, Infineon announced an
eWLB licensing agreement with Advanced Semiconductor Engineering
Inc. (ASE; Kaohsiung, Taiwan), though products from the union have
yet to emerge. Infineon has said the redistributed packaging
approach is well-suited for wireless products, with cellphone
transceivers as a likely target.

Freescale has built a pilot RCP
production line in Tempe, Ariz., devoting considerable energies
to proving out the RCP approach. Chhabra said Freescale is in
discussions with commercial packaging companies that would provide
Freescale’s customers with a second-source capability and
satisfy the “fabless companies, IDMs and OEMs requesting a
source for this technology.” Chhabra said “we are in
active discussions with several potential partners on having
high-volume capacity available.”

A united front with Freescale,
Infineon, and commercial packaging companies also would encourage
equipment vendors to develop the production-worthy tools needed to
perfect the redistributed packaging approach.

“If Freescale and Infineon
develop a converged roadmap for redistributed packaging, many
companies would use it,” said Jim Walker, the packaging
technology analyst at Gartner Inc.

Intel Corp. promoted a build-up
layer technology for a couple of years and then abandoned its
effort in 2001 for lack of support, he said. Since then,
Motorola/Freescale, Siemens/Infineon, and Tessera Inc. have
developed their flavors of the redistributed approach,
which supports embedded resistors and capacitors as well as
active devices.

“Companies are trying to
figure out where to get their value-add in the manufacturing
process. Some companies are working on business models that involve
a convergence of packaging and the front-end fab,” involving wafer
level packaging and including through silicon vias (TSVs), Walker
said.

Thermal Issues
Loom

The materials issues are one
challenge, but heat is the bigger problem. “Not many people
have addressed the thermal management issues, which are going to be
very big,” Walker said. A decade ago, die were 300-400
µm thick. The active circuitry was in the top 10 µm,
and the rest of the thick die acted as a thermal heat sink. With
wafer level packaging and the redistribution approaches, die now
are.being thinned to 50-75 µm. “There no longer is a
heat sink to take heat down into the board or the system substrate.
All the heat is on the face, and then we stack a die on
that,” Walker said

Also, molding compounds in
traditional packaging, which consist largely of inert materials,
further help to dissipate heat away from surface of the die. While
integrated companies such as Freescale or Infineon have an
advantage in that their internal design teams can take thermal
issues into account when targeting redistributed forms of
packaging, Walker said the thermal issues remain formidable
nevertheless. “If you are putting another chip right on top
of another, you have got to dissipate that heat from these thinned
die. Sure, Freescale is putting a coating on there, a
redistribution polyimide. But it is just a coating, and unlike
molding compound they don’t have any materials to pull the
heat away, and the heat has got to go somewhere,” he
said.

The issue is particularly difficult
to solve for large-die microprocessors with hot spots. While
embedded memory doesn’t get as hot, stacking memory on top of
a CPU with all of its I/O going represents “thermal gradiants
in the X and Y, as well as the Z, dimension. CtE (co-efficient of
thermal expansion) issues also can affect reliability, and they all
affect performance characteristics,” Walker said.

“This is a concern I have with
some of the thinner die. There is nothing to draw the heat out. We
are going to have the same problem with TSVs. The hole is a void,
and yes, there can be plating through the hole. In essence, we have
an air pocket with a different expansion than silicon. Then
companies have to figure out how to stack TSV silicon chips on top
of each other. The challenges are there, and we will overcome them,
but companies know they can’t just take a chip and stack it
on top of another without knowing all the parameters. The package,
design, and manufacturing, all has to be designed as a
system.”