Perspectives From the Leading Edge
Leading-edge microelectronics activity and real-world insight by Philip Garrou
ESI acquires XSil IP and Assets
Other information sources / blogs may be satisfied giving you headlines and write-ups right off the newswire, but at PFTLE we seek to give you a lot more. So when we saw the outcome of the XSil bankruptcy a few weeks ago, we held off presenting it to you till we could speak directly to ESI and get a better idea of what their plans are. Long time readers know that PFTLE has been followi ...... Read More
Comments (0)The European Microelectronics & Packaging Conf (EMPC)
The 17th IMAPS Europe meeting was held a week ago in Rimini Italy. I last attended this meeting in Venice 12 years ago when I was President of IMAPS. In Europe IMAPS consists of 12 independent chapters: Germany, UK, Benelux, Czech & Slovak, France, Hungary, Israel, Italy, Nordic, Poland, Romania, Slovenia and Russia with a coordinating body known as the European Liaiso ...... Read More
Comments (0)SUSS MicroTec Bonders for Temporary and Permanent 3D Bonding Solutions
SUSS MicroTec and 3M have announced an agreement where Suss offers 3M’s temporary bonding process as part of their new SUSS 300 mm bonder line. You may have seen that headline on Monday. When you come to PFTLE you come for more than the headlines - you come for the technology behind the headlines and in this case we have it ! The new SUSS XBC300 cluster tool allows connection of up to ...... Read More
Comments (0)Start Ups with a Future
Continuing with recent presentations from the 2009 ECTC Conference in San Diego. Replisaurus Replisaurus has previously been discussed in PFTLE “ECPR - Electrochemical Pattern Replication”, 01/06/2008 and “Replisaurus Moving Forward Despite Harsh Economic Environment” 01/24/2009. Their new presentation “Novel Multi-layer Wiring Build-up using Electrochemica ...... Read More
Comments (0)3D IC at the 2009 ECTC
Sandia W TSV Process Sandia gave a very detailed presentation on their W TSV process. They demonstrated 2 µm diameter/45 µm deep TSVs on 20 µm pitch for an interconnect density of 250,000/cm2. Thermal oxidation of silicon is used to form the dielectric isolation. After via etching and dielectric isolation, they fill the interconnect holes with CVD silicon. The total silicon th ...... Read More
Comments (0)Experience or Prejudice? The Case for Silicon Interposers
My past corporate manager once made me take a psychobabble course entitled something like “You Are Who You Were When.” Notice I said “made” because I was, and still am, notoriously against anything that smells of psychobabble or political correctness. My credo is simply “Say what you mean and mean what you say” (adapted from the motto of Horton the ...... Read More
Comments (0)ECTC 2009 San Diego
The Electronic Component Technology Conference (ECTC) , is sponsored by the IEEE’s Component, Packaging and Manufacturing Technology Society (CPMT) and the EIA (Electronic Industry Association). For the Component and Packaging community this is the pre-eminent conference on such topics during the year. Their 59th annual meeting was held last week in San Diego. Despite the economy ...... Read More
Comments (1)Temporary Bonding for 3-D IC Thinning and Backside Processing
As we have discussed many times before, one of the important aspects of 3-D technology process flow is how you handle wafer thinning. A typical process flow for temporary bonding involves the carrier wafer and/or the device wafer being coated with an adhesive, bonding of the device and handle wafers, processing of the wafers and then removal of the carrier, hopefully without ever having to ...... Read More
Comments (0)NXP Sells Off PICS Passive Integration
Philips spun out its semiconductor division and a lot of its debt as NXP in the fall of 2006. Ever since then, parts of the company have been sold off to lighten this debt load. Shortly after NXP announced the joint venture of its wireless division with STMicroelectronics, and the subsequent sale of this venture to ST-Ericsson, last summer, its 150 mm wafer plant in Caen, France, was put up ...... Read More
Comments (0)Nice DATE
Design, Automation and Test in Europe (DATE) was held this year in Nice, France, which is certainly a NICE place for a DATE. I think that’s two double entendres in one sentence, certainly a record for me. As part of this year’s conference, Erik Jan Marinissen, IMEC; Yann Guillou, ST-Ericsson; and Geert Van der Plas, IMEC held a session entitled “3D Integration &# ...... Read More
Comments (0)All Silicon System Integration Dresden (ASSID) – A 300 mm 3-D IC Line for Germany
Many of you will have already seen the press release that Dresden will be the site of a Fraunhofer 3-D silicon research institute. I decided to dig a little deeper, so I contacted colleagues in Berlin and Munich to learn more. The newest Fraunhofer center, All Silicon System Integration Dresden (ASSID), will report into old friend Herbert Reichl, head of Fraunhofer IZM, which has bra ...... Read More
Comments (0)TSMC Reconfirms Plans for Fab-Based TSV
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) held its 2009 technical symposium this past Tuesday in San Jose with the theme, “Collaborate to Innovate.” Although I wasn’t there, I did get a complete debriefing from my colleague Jan Vardaman, CEO of TechSearch Inc., who was on hand. Depending on your frame of reference, there were many things to be interested ...... Read More
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