RTI 3D ASIP, Aviza, Jenoptik Laser Dicing
RTI 3D ASIP
It was 2004 when RTI held its first 3D conference, long before 3D became the buzz word it is today. Last year I suggested that 3-D Architectures for Semiconductor Integration and Packaging was quite a mouthful and should be dubbed “3D ASIP.” With every IC and packaging conference in the world now vying for 3D papers, 3D ASIP remains as the one meeting focused on leading edge technical advances and key infrastructure developments.
This year’s meeting will be chaired by old friend Bob Lanzone (Amkor) and I . We think we’ve put together another great program for you. In the pre-conference symposium Paul Ho, U Texas will be covering the thermo-mechanical aspects of 3D TSV; Nagesh Vodrahalli of Allvia will be showing us their take on the implementation and future outlook of 3D IC; Claudio Truzzi from Alchimer will be giving us the in-depth details on how their wet processing technology can lower the costs involved with filling TSV; and I will be covering … well … the key 3D themes that I cover for you in PFTLE.
3D ASIP keynote sessions are reserved for those speakers whose companies hold the ability to shift the direction of 3D IC with a single presentation. This year we have chosen Douglas Yu of TSMC, Jerry Bautista of Intel and John Knickerbocker of IBM from the foundry and IDM world; and Ho-Ming Tong of ASE, Raj Pendse of STATS ChipPAC and Ron Hoemoeller of Amkor from the OSAT world to tell us where things are and where they are going.
The ever popular marketing session highlighted by marketers TechSearch International and Yole Developpement is again scheduled. This is the only chance you’ll have this year to compare numbers and ask the two why their numbers don’t match!
Another session that should be popular will involve a discussion of temporary bonding / thin wafer handling / permanent bonding by the 3 giants in the field EV, Suss and TOK. First time they have ever presented back to back to back so you can compare their solutions.
Hope you plan on being in Burlingame CA on Dec 9 - 11 to learn, mingle and enjoy. For a full program see http://techventure.rti.org.
Aviza Acquired by Sumitomo Precision Products
Some of you may have caught the LexisNexis newswire last month when it was announced that Sumitomo Precision Products (SPP) acquired Aviza Technologies.
In 1995 SPP acquired Surface Technology Systems (STS), which was and continues to be a leader in silicon DRIE “Bosch” etching for the MEMS and 3D communities. Aviza will be combined with STS into a new business unit named Sumitomo Process Technology Systems (SPTS).
We have discussed the Aviza solution for insulation, barrier and seed deposition previously (see PFTLE “Optimism vs Reality; Semantics or Lost in Translation??,” 10/11/2009). Further data on their low temp oxide deposition process was given recently at Semicon Taiwan. The 150°C dep temp with 7.5 MV/cm breakdown voltage and 5 × 10-8 A/cm2 leakage current is certainly an accomplishment.
In addition they are now detailing an MOCVD TiN barrier dep that can deposit 50 nm/min at 250°C.
Laser Dicing
Jenoptik Laser Technologies has developed a technique called TLS (thermal laser separation), which is used to cleanly dice thin and/or brittle materials. They recently described this technique at the IMAPS 2009 Int Symp on Microelectronics, which just finished up in San Jose.
TLS is a two-step process consisting of scribe and cleave. The initial scribe can be done with a diamond tool or a low power pulsed laser. After the initial scribe, cleaving is initiated by creating thermal stresses by a combination of laser heating and cooling (gas or liquid aerosol mix). The laser, optical system and cooling nozzle are integrated into a single unit that transverses the wafer along the desired separation line. As the heated material expands, pressure forces occur within the heated zone (TF I). The laser beam is immediately followed by a cooling spot, which causes the material to shrink in the cooling zone (TF II). At the overlay of the two zones the forces are additive and draw the crack through the material (see the figure below).
Ablation lasers have been used for dicing to reduce street widths. Unlike ablation lasers, with TLS there is no HAZ region (heat affected zone) and no residues from the melted and evaporated materials.
Si wafers from 30 - 250 µm thick have been diced with street widths between 30 and 75 µm. 100 mm GaAs wafers have been separated into die 1 × 0.8 mm.
For all the latest on 3D IC and advanced packaging stay linked to PFTLE………..
Yu Yang commented:
Cool. But my concern on laser dicing is two-folded: first is the heat affected zone, which seems to be solved; second is the rough surface, which might be a big issue for such thin dies in their packages.
