Taiwanese Focus on 3D IC
PFTLE recently covered 3D activities at ITRI (see PFTLE, “3D IC at ITRI,” 09/24/2009). As an update to that information, let’s discuss the recent presentation of Dr. Ian Yi-Chen Chan, VP and General Director of ITRI , who offered significant new information about this effort.
The Industrial Technology Research Institute (ITRI) has the stated goal of helping to expedite future industrial technology in Taiwan. With three of the top five foundries and three of the top five OSATS (four if you include a portion of Amkor) in the world within her borders, it is logical that Taiwan would see a need to be prepared for any and all changes in the IC world.
| Foundries | OSATS | ||||||
| Company | Country | Rank | 2008 Revenue(B$)* | Company | Country | Rank | 2008 Revenue(B$)** |
| TSMC | Taiwan | 1 | 10.3 | ASE | Taiwan | 1 | 3.0 |
| UMC | Taiwan | 2 | 2.9 | Amkor | US | 2 | 2.7 |
| Chartered | Singapore | 3 | 1.8 | SPIL | Taiwan | 3 | 1.92 |
| SMIC | China | 4 | 1.4 | STATSChipPAC | Singapore | 4 | 1.65 |
| Vanguard | Taiwan | 5 | 0.51 | Powertech | Taiwan | 5 | 0.95 |
* iSupply (June 2009); ** Gartner (Feb 2009)
Through their Advanced Stacked-System Technology and Application Consortium (Ad-STAC), ITRI is aligning member companies and putting the necessary equipment in place. Key to these activities is the installation of a complete 300 mm 3D IC line. By their published schedule (below), equipment installation should be complete by the end of this year with base line process start up occurring in early 2010.
| Operation | Equipment | Function | Schedule (2009) |
| Lithography | Aligner | pattern exposure | Nov |
| Track | PR/polymer coat & develop | Nov | |
| Etching | DRIE etcher | Si etch | June |
| l dry etch | Metal etch (Al, barrier) | Dec | |
| Dry etch | Oxide/nitride etching | Dec | |
| Thin Film | PECVD | Oxide TSV isolation | Dec |
| PVD (sputter) | Copper seed / barrier dep | Dec | |
| ECD Cu | Cu TSV plating | Nov 2008 | |
| CMP | CMP | Cu, W, pSi polishing | Dec |
| Micro bump | ECP - solder | Solder bump plating | Dec |
| Bonding | Bond aligner | Pre bond alignment | March 2010 |
| Wafer to wafer bonder | Wafer to wafer bonding | March 2010 | |
| Chip on wafer bonder | Chip to wafer bonding | Oct |
Dr. Chan sees 3D IC combining with SoC (system on chip) and SiP (system in package) to be the three enablers of high performance, high density, small form factor products of the future.
Whereas design, fab, package and test are treated as separate functions in today’s traditional IC manufacturing, Dr. Chan foresees that 3D IC technology will lead to a restructuring of these operations in the overall value chain. He envisions a blurring of the lines between IC design, fab, package and test operations. New companies may develop to meet the needs of the new 3D IC infrastructure or current companies may develop additional skills.
While everyone else in the world was complaining that the technology cost for bumping and WLP was not low enough for mass production, Taiwan stepped up, put capacity in place and made bumping and WLP for portable products a reality. Will they do the same for 3D IC?? A lot of people certainly think so. Professor Kuan-Neng Chen from the National Chiao Tung University, and a former IBM researcher on 3D IC, said, “I can see ITRI’s efforts on behalf of Taiwanese foundries and OSATS and their global materials and equipment partners will bring Taiwan into the lead on 3D IC technology and allow mass production. When this occurs, this will be something they can be very proud of.”
Next week we will finish up on the IEEE 3D Conference and look ahead to the RTI “3D Architectures for Semiconductor Integration and Packaging” (ASIP) Conference in December.
For all the latest in 3D IC and advanced packaging stay linked to Perspectives from the Leading Edge…………………………
PFTLE commented:
stacked - If what you mean by waiting is that you cannot buy wafers with TSV now or that they will be specialty items when first introduced - you are correct, but that is true for all new technologies.
In terms of one bad TSV scrapping the die - NO. Check out past blogs for description of Samsung 8 Gb DDR3 stack with TSV. Redundant TSV are added so that this will not occur.
PFTLE commented:
"repackaging" - so tell me how you really feel !
Just kidding - thanks for the support and what your saying is correct, anyone that does not think this will be pervasive is wrong. Next time you leave a response, pick a stronger name like "3D supporter" !
PFTLE commented:
"guest" - I sugegst you read all my blogs and the book "Handbook of 3D Integration" and then ask the question again. 3-D IC is not repackaging. You need thinning, bonding and TSV. Thinning certainly has been developed for other technologies but bonding and TSV are unique to this technology. CMOS image sensors with backside TSV have already happened. Memory stacks [DRAM]and then memory on logic will be coming soon (again read the past blogs). It is my position that TSV will become routine and will be mainly inserted during foundry production of the chips so I think TSMC and UMC will eventually be in this business along with Chartered, SMIC and the big IDMs.
stacked commented:
I still have a hard time to imagine waiting for a DRAM wafer or a CPU wafer. If one TSV fails irreparably, scrap everything? Doesn’t sound right.
Repackaging? commented:
I have to respond to the comment about repackaging of “mature technologies”? Are you saying that submicron, wafer to wafer alignment is repackaging? what about 1.5um pitch interconnect between distint wafer levels bonded at very low tempertures? What about buried vias before metal one so you can thin to expose? You make it sound like this is falling off a log…so why haven’t any of these guys fallen off yet? Oh wait…maybe ALD is simply the repackaging of standard deposition technologies? There will be ZERO innovation in micro and nano electronics in the coming years that does not involve 3DICs in some way.
guest commented:
3DIC is just a repackaging of mature technologies. What type of 3DIC products are possible? Will there be a spin-off foundry from ITRI just dedicated to TSVs and wafer stacking integration?
